AK1544 Datasheet, PDF (15/37 Pages) Asahi Kasei Microsystems – 1300MHz Integer-N Frequency Synthesizer

[AK1544]
4.2 Digital Lock Detect
In the digital lock detect, the [LD] pin outputs is ”Low” every time when the frequency is set. And the [LD] pin outputs is
“High” (which means the locked state) when a phase error smaller than T is detected for N times consecutively. If the
phase error is larger than T is detected for N times consecutively then the [LD] pin outputs is “High” and then the [LD] pin
outputs is “Low”(which means the unlocked state).
The threshold counts for lock detection N could be set by D[18:17]={LDCNTSEL[1:0]} in <Address4>.
{LDCNTSEL[1:0]} settings and corresponding counts (N) are as follows:
00: N = 7
01: N = 15
10: N = 31
11: N = 63
The lock detect signal is shown below:
Reference clock
PFD clock
VCO divider clock
Phase detector output
Lock detect result
ï¼´
Invalid _Valid
Valid
Valid
Invalid
Fig. 8 Lock Detect Operations
Invalid ^Valid
MS1350-E-01
15
2013/03