AK7736BVQ Datasheet, PDF (14/22 Pages) HuaXinAn Electronics CO.,LTD – Audio/HF DSP

[AK7736B]
■ Microprocessor Interface
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS=0V; CL=20pF)
Parameter
Symbol
min
typ
Microprocessor Interface Signal
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL 200
SCLK High Level Width
tSCLKH 200
Microprocessor → AK7736B
CSN High Level Width
tWRQH 500
From CSN “↑” to PDN “↑”
tRST
600
From PDN “↑” to CSN “↓”
tIRRQ
1
From CSN “↓” to SCLK “↓”
tWSC
500
From SCLK “↑” to CSN “↑”
tSCW
800
SI Latch Setup Time
tSIS
200
SI Latch Hold Time
tSIH
200
AK7736B → Microprocessor
Delay Time from SCLK “↓” to SO Output
tSOS
Hold Time from SCLK “↑” to SO Output (Note 29) tSOH
200
90H
Note 29. Except when input the eighth bit of the command code.
max Unit
2.1 MHz
ns
ns
ns
ns
ms
ns
ns
ns
ns
200
ns
ns
■ I²C-BUS Interface
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS=0V; CL=20pF)
Parameter
Symbol
min typ max Unit
I2C Timing
SCL clock frequency
fSCL
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
s
Start Condition Hold Time (prior to first Clock pulse) tHD:STA
0.6
s
Clock Low Time
tLOW
1.3
s
Clock High Time
tHIGH
0.6
s
Setup Time for Repeated Start Condition
tSU:STA
0.6
s
SDA Hold Time from SCL Falling
tHD:DAT
0
0.9 s
SDA Setup Time from SCL Rising
tSU:DAT
0.1
s
Rise Time of Both SDA and SCL Lines
tR
0.3 s
Fall Time of Both SDA and SCL Lines
tF
0.3 s
Setup Time for Stop Condition
tSU:STO
0.6
s
Pulse Width of Spike Noise Suppressed By Input Filter tSP
0
50
ns
Capacitive load on bus
Cb
400 pF
MS1562-E-00-PB
- 14 -
2013/10