AK7736BVQ Datasheet, PDF (13/22 Pages) HuaXinAn Electronics CO.,LTD – Audio/HF DSP

[AK7736B]
■ Serial Data Interface
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V; CL=20pF)
Parameter
Symbol min typ
DSP Section Input SDIN1, 2A, 2B, 2C, 3, 4 (Note 19)
75H
Delay Time from BITCLK1 “↑” to LRCLK1 (Note 20) tBLRD 20
76H
Delay Time from LRCLK1 to BITCLK1 “↑” (Note 20) tLRBD 20
7H
Serial Data Input Latch Setup Time
tBSIDS 80
Serial Data Input Latch Hold Time
tBSIDH 80
SRC Section Input SDIN3
Delay Time from BITCLKI3 “↑” to LRCLKI3 (Note 21) tBLRD 20
78H
Delay Time from LRCLKI3 to BITCLKI3 “↑” (Note 21) tLRBD 20
79H
Serial Data Input Latch Setup Time
tBSIDS 40
Serial Data Input Latch Hold Time
tBSIDH 40
FSCONV Section Input SDIN4
(Note 22)
80H
Delay Time from BITCLKI2 “↑” to LRCLKI2 (Note 23) tBLRD 20
81H
Delay Time from LRCLKI2 to BITCLKI2 “↑” (Note 23) tLRBD 20
82H
Serial Data Input Latch Setup Time
tBSIDS 40
Serial Data Input Latch Hold Time
tBSIDH 40
Output SDOUT1, SDOUT2, SDOUT3, SDOUT4
BITCLKO Frequency
(Note 24) fBCLK
64
83H
BITCLKO Duty Factor
(Note 24)
50
84H
Delay Time from BITCLKO “↓” to LRCLKO (Note 25) tMBL
-20
85H
Delay Time from LRCLK1 to Serial Data Output (Note 26) tLRD
86H
Delay Time from BITCLK1“↓” to Serial Data Output
tBSOD
(Note 27)
87H
Delay Time from LRCLKO to Serial Data Output (Note 26) tLRD
8H
Delay Time from BITCLKO “↓” to Serial Data Output
tBSOD
(Note 28)
89H
SDINn → SDOUTn (n=1, 2A, 2B, 2C, 3, 4)
Delay Time from SDINn to SDOUTn Output
tIOD
Note 19. In CKM mode 4, these are the time from LRCKLI2 or BITCLKI2.
Note 20. When BITCLK1 polarity is inverted, delay time is from BITCLK1 “↓”.
Note 21. When BITCLKI3 polarity is inverted, delay time is from BITCLKI3 “↓”.
Note 22. Except CKM mode 4.
Note 23. When BITCLKI2 polarity is inverted, delay time is from BITCLKI2 “↓”.
Note 24. Except slave mode.
Note 25. When BCKOP bit = “1”, delay time is from BITCLKO “↑”.
Note 26. Except I²S compatible mode.
Note 27. When BITCLK1 polarity is inverted, delay time is from BITCLK1 “↑”.
Note 28. When BITCLKO polarity is inverted, delay time is from BITCLKO “↑”.
max Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fs
%
40 ns
80 ns
80 ns
80
80
60 ns
MS1562-E-00-PB
- 13 -
2013/10