AK7736BVQ Datasheet, PDF (12/22 Pages) HuaXinAn Electronics CO.,LTD – Audio/HF DSP

[AK7736B]
10. Switching Characteristics
■ System Clock
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V; CL=20pF)
Parameter
Symbol
min
typ max
a) with a Crystal Oscillator
CKM[2:0]bits=0h
fXTI
11.2896
MHz
12.288
CKM[2:0]bits=1h
fXTI
16.9344
MHz
18.432
b) with an External Clock
Duty Cycle
40
50
60
%
CKM[2:0]bits=0h,2h
fXTI
11.0
11.2896 12.4 MHz
12.288
CKM[2:0]bits=1h
fXTI
16.5
16.9344 18.6 MHz
18.432
LRCLK1 Frequency
(Note 14)
fs
8
70H
96
kHz
BITCLK1 Frequency
(Note 15)
71H
32,48,64
fs
High Level Width
tBCLKH 64
ns
Low Level Width
tBCLKL 64
ns
Frequency
fBCLK
0.23
3.072
6.2
MHz
LRCLKI2 Frequency (FSCONV) (Note 16) fs
44.1
72H
48
kHz
BITCLKI2 Frequency (FSCONV) (Note 17)
73H
32,48,64,12
fs
8
High Level Width
tBCLKH 64
ns
Low Level Width
tBCLKL 64
ns
Frequency
fBCLK
1.25
3.072
6.2
MHz
LRCLKI3 Frequency (SRC)
fs
8
96
kHz
BITCLKI3 Frequency (SRC)
32,48,64,12
fs
8
High Level Width
tBCLKH 32
ns
Low Level Width
tBCLKL 32
ns
Frequency
fBCLK
0.23
3.072
12.4 MHz
Note 14. LRCLK1 frequency and sampling rate (fs) should be the same.
Note 15. When BITCLK1 is used as a master clock reference clock, it should be synchronized with LRCLK1,
and its frequency should be fixed.
Note 16. fs=8~48kHz in CKM mode 4.
Note 17. 128fs is inhibited in CKM mode 4.
■ Power Down
(Ta= -40°C to 85°C; VDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, VSS =0V)
Parameter
Symbol
min
typ
max Unit
PDN
(Note 18)
tRST
600
ns
74H
Note 18. The PDN pin must be “L” when power up the AK7736B.
MS1562-E-00-PB
- 12 -
2013/10