AK4388A Datasheet, PDF (14/18 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 2ch ΔΣ DAC

[AK4388A]
SYSTEM DESIGN
Figure 11 shows the system connection diagram. An evaluation board (AKD4388A) is available for fast evaluation as
well as suggestions for peripheral circuitry.
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Mode
Setting
Digital Ground
1 MCLK
DZF 16
2 BICK
DEM 15
3 SDTI
VDD 14
4 LRCK _AK4388A VSS 13
5 RSTN
VCOM 12
6 SMUTE
AOUTL 11
7 ACKS
AOUTR 10
8 DIF0
DIF1 9
Optional External
Mute Circuits
0.1u ⁺ 10u
10u
+
Analog
Supply 5V
Lch Out
Rch Out
Analog Ground
Figure 11. Typical Connection Diagram
Notes:
- LRCK = fs, BICK=64fs.
- When AOUT drives capacitive load, a resistor must be connected in series between AOUT and capacitive load.
- All input pins except DIF1 and DEM pins must not be left floating.
MS1008-E-02
- 14 -
2010/09