AK4388A Datasheet, PDF (13/18 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 2ch ΔΣ DAC

[AK4388A]
■ Reset Function (MCLK, LRCK or BICK stop)
When the MCLK, LRCK or BICK stops, the digital circuit of the AK4388A is placed in power-down mode. When the
MCLK, LRCK and BICK are restarted, power-down mode is released and the AK4388A returns to normal operation
mode.
RSTN pin
Internal
State
Power-down
Normal Operation
D/A In
(Digital)
Power-down
D/A Out
(Analog)
VCOM
(3)
<Case1:MCLK Stop>
Clock In
MCLK, BICK, LRCK
GD (1)
External
MUTE
(5)
Digital Circuit Power-down
Normal Operation
(2)
(3)
(4)
(3)
GD (1)
MCLK Stop
(5)
<Case2:LRCK Stop>
Clock In
MCLK, BICK, LRCK
External
MUTE
(5)
LRCK Stop
(5)
(5)
<Case3:BICK Stop>
Clock In
MCLK, BICK, LRCK
External
MUTE
(5)
BICK Stop
(5)
(5)
Notes.
(1) The analog output corresponding to a specific digital input has group delay (GD).
(2) Digital data can be stopped. The click noise, after MCLK, LRCK and BICK are input again, can be reduced by
inputting the “0” data during this period.
(3) Click noise occurs within 20usec or 20usec +3 ~ 4LRCK from the riding edge (“↑”) of the RSTN pin or MCLK
inputs. Click noise also occurs within 20usec when MCLK, LRCK or BICK is stopped.
(4) The analog output becomes idle voltage when MCLK is stopped. It becomes VCOM voltage if LRCK or BICK is
stopped when MCLK is input.
(5) Mute the analog output externally if click noise (3) adversely affect system performance.
Figure 10. Clock Stop Sequence
MS1008-E-02
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2010/09