AK4388A Datasheet, PDF (11/18 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 2ch ΔΣ DAC

[AK4388A]
■ Zero Detection
When the input data at both channels are continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H”. The DZF
pin immediately returns to “L” if input data of both channels are not zero (Figure 8).
■ Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles, the
attenuation is discontinued and returned to 0dB in the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
SMUTE pin
0dB
Attenuation
1024/fs
(1)
1024/fs
(3)
-∞
GD
GD
(2)
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) 1024LRCK cycles (1024/fs) at input data is attenuated to -∞.
(2) The analog output corresponding to the digital input has group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returned to ATT level by
the same cycle.
(4) When the input data at both channels are continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H”. The
DZF pin immediately returns to “L” if input data are not zero.
Figure 8. Soft Mute and Zero Detection
MS1008-E-02
- 11 -
2010/09