DSP1629 Datasheet, PDF (94/126 Pages) Agere Systems – DSP1629 Digital Signal Processor

DSP1629 Digital Signal Processor
Data Sheet
March 2000
10 Timing Characteristics for 3.0 V Operation (continued)
VOH–
ICK _VOL–
VOH–
ILD _VOL–
VIH–
DI _VIL–
VOH–
IBF _VOL–
t101
t76a
*
t77
t78
B0
B1
* ILD goes high during bit 6 (of 0:15), N = 8 or 16.
Figure 31. SIO Active Mode Input Timing Diagram
BN – 1
B0
t79
5-4778 (F)
Table 98. Timing Requirements for Serial Inputs
Abbreviated Reference
t77
t78
Parameter
Data Setup (valid to high)
Data Hold (high to invalid)
Table 99. Timing Characteristics for Serial Outputs
Abbreviated Reference
t76a
t101
t79
Parameter
ILD Delay (high to low)
ILD Hold (high to invalid)
IBF Delay (high to high)
Min
7
0
Min
—
3
—
Max
—
—
Max
35
—
35
Unit
ns
ns
Unit
ns
ns
ns
94
Lucent Technologies Inc.