DSP1629 Datasheet, PDF (1/126 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Sheet
March 2000
DSP1629 Digital Signal Processor
1 Features
s Optimized for digital cellular applications with a bit
manipulation unit for higher coding efficiency.
s On-chip, programmable, PLL clock synthesizer.
s 10 ns and 16.7 ns instruction cycle times at 3.0 V, and
19.2 ns and 12.5 ns instruction cycle times at 2.7 V,
respectively.
s Mask-programmable memory map option: The
DSP1629x16 features 16 Kwords on-chip dual-port
RAM. The DSP1629x10 features 10 Kwords on-chip
dual-port RAM. Both feature 48 Kwords on-chip ROM
with a secure option.
s Low power consumption:
— <1.9 mW/MIPS typical at 2.7 V.
s Flexible power management modes:
— Standard sleep: 0.2 mW/MIPS at 2.7 V.
— Sleep with slow internal clock: 0.7 mW at 2.7 V.
— Hardware STOP (pin halts DSP): <20 µA.
s Mask-programmable clock options: small signal, and
CMOS.
s 144 PBGA package (13 mm x 13 mm) available.
s Sequenced accesses to X and Y external memory.
s Object code and pin compatible with the DSP1627.
s Single-cycle squaring.
s 16 x 16-bit multiplication and 36-bit accumulation in
one instruction cycle.
s Instruction cache for high-speed, program-efficient,
zero-overhead looping.
s Dual 25 Mbits/s serial I/O ports with multiprocessor
capability:
— 16-bit data channel, 8-bit protocol channel.
s 8-bit parallel host interface:
— Supports 8- or 16-bit transfers.
— Motorola^* or Intel^† compatible.
s 8-bit control I/O interface.
s 256 memory-mapped I/O ports.
s IEEE^‡ P1149.1 test port (JTAG boundary scan).
* Motorola is a registered trademark of Motorola, Inc.
† Intel is a registered trademark of Intel Corporation.
‡ IEEE is a registered trademark of The Institute of Electrical
and Electronics Engineers, Inc.
s Full-speed in-circuit emulation hardware develop-
ment system on-chip.
s Supported by DSP1629 software and hardware
development tools.
2 Description
The DSP1629 is Lucent Technologies Microelectronics
Group’s first digital signal processor offering 100 MIPS
operation at 3.0 V and 80 MIPS operation at 2.7 V with a
reduction in power consumption. Designed specifically
for applications requiring low power dissipation in digital
cellular systems, the DSP1629 is a signal-coding device
that can be programmed to perform a wide variety of
fixed-point signal processing functions. The device is
based on the DSP1600 core with a bit manipulation unit
for enhanced signal coding efficiency. The DSP1629 in-
cludes a mix of peripherals specifically intended to sup-
port processing-intensive but cost-sensitive applications
in the area of digital wireless communications.
The DSP1629x16 contains 16 Kwords of internal dual-
port RAM (DPRAM), which allows simultaneous access
to two RAM locations in a single instruction cycle. The
DSP1629x10 supports the use of 10 Kwords of DPRAM.
Both devices contain 48 Kwords of internal ROM (IROM).
The DSP1629 is object code compatible with the
DSP1627 while providing more memory. The DSP1629 is
pin compatible with the DSP1627. Note that TRST (JTAG
test reset) replaces a VDD pin.
The DSP1629 supports 2.7 V, and 3.0 V operation and
flexible power management modes required for portable
cellular terminals. Several control mechanisms achieve
low-power operation, including a STOP pin for placing the
DSP into a fully static, halted state and a programmable
power control register used to power down unused on-
chip I/O units. These power management modes allow
for trade-offs between power reduction and wake-up la-
tency requirements. During system standby, power con-
sumption is reduced to less than 20 µA.
The on-chip clock synthesizer can be driven by an exter-
nal clock whose frequency is a fraction of the instruction
rate.
The device is packaged in a 144-pin PBGA, a 100-pin
BQFP, or a 100-pin TQFP and is available with 10 ns and
16.7 ns instruction cycle times at 3.0 V, and 19.2 ns and
12.5 ns instruction cycle times at 2.7 V, respectively.