DSP1629 Datasheet, PDF (50/126 Pages) Agere Systems – DSP1629 Digital Signal Processor

DSP1629 Digital Signal Processor
Data Sheet
March 2000
5 Software Architecture (continued)
Table 28. Parallel Host Interface Control (phifc) Register
Bit
15—7
6
5
4
Field
RSVD
PSOBEF PFLAGSEL PFLAG
3
PBSELF
2
PSTRB
1
PSTROBE
0
PMODE
Field
PMODE
PSTROBE
PSTRB
PBSELF
PFLAG
PFLAGSEL
PSOBEF
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
8-bit data transfers.
16-bit data transfers.
Intel protocol: PIDS and PODS data strobes.
Motorola protocol: PRWN and PDS data strobes.
When PSTROBE = 1, PODS pin (PDS) active-low.
When PSTROBE = 1, PODS pin (PDS) active-high.
In either mode, PBSEL pin = 0 → pdx0 low byte. See Table 7.
If PMODE = 0, PBSEL pin = 1 → pdx0 low byte.
If PMODE = 1, PBSEL pin = 0 → pdx0 high byte.
PIBF and POBE pins active-high.
PIBF and POBE pins active-low.
Normal.
PIBF flag ORed with POBE flag and output on PIBF pin; POBE pin un-
changed (output buffer empty).
Normal.
POBE flag as read through PSTAT register is active-low.
Table 29. Interrupt Control (inc) Register
Bit
15
Field JINT*
14—11
RSVD
10
9
8 7—6 5—4
3
2
1
0
OBE2 IBF2 TIME RSVD INT[1:0] PIBF POBE OBE IBF
* JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Lucent Technologies development system tools.
Encoding: A 0 disables an interrupt; a 1 enables an interrupt.
Table 30. Interrupt Status (ins) Register
Bit
15
Field JINT
14—11
RSVD
10
9
OBE2 IBF2
8
TIME
7—6
RSVD
5—4
INT[1:0]
3
PIBF
2
1
0
POBE OBE IBF
Encoding: A 0 indicates no interrupt. A 1 indicates an interrupt has been recognized and is pending or being ser-
viced. If a 1 is written to bits 4, 5, or 8 of ins, the corresponding interrupt is cleared.
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