DSP1629 Datasheet, PDF (19/126 Pages) Agere Systems – DSP1629 Digital Signal Processor

Data Sheet
March 2000
4 Hardware Architecture (continued)
Table 6. Data Memory Maps
1629x16 Data Memory Map (Not to Scale)
Decimal
Address
0
Address in
r0, r1, r2, r3
0x0000
Segment
DPRAM[1:16]
DSP1629 Digital Signal Processor
1629x10 Data Memory Map (Not to Scale)
Decimal
Address
0
Address in
r0, r1, r2, r3
0x0000
Segment
DPRAM[1:10]
10K
0x2800
Reserved
(6 K)
16K
16,640
0x4000
0x4100
IO
ERAMLO
16K
16,640
32K
0x4000
0x4100
0x8000
IO
ERAMLO
ERAMHI
32K
0x8000
ERAMHI
64K – 1
0xFFFF
On the data memory side (see Table 6), the 1K banks
of dual-port RAM are located starting at address 0. Ad-
dresses from 0x4000 to 0x40FF reference a 256-word
memory-mapped I/O segment (IO). Addresses from
0x4100 to 0x7FFF reference the low external data RAM
segment (ERAMLO). Addresses above 0x8000 refer-
ence high external data RAM (ERAMHI).
64K – 1
0xFFFF
Wait-States
The number of wait-states (from 0 to 15) used when ac-
cessing each of the four external memory segments
(ERAMLO, IO, ERAMHI, and EROM) is programmable
in the mwait register (see Table 36). When the program
references memory in one of the four external seg-
ments, the internal multiplexer is automatically switched
to the appropriate set of internal buses, and the associ-
ated external enable of ERAMLO, IO, ERAMHI, or
EROM is issued. The external memory cycle is auto-
matically stretched by the number of wait-states config-
ured in the appropriate field of the mwait register.
Lucent Technologies Inc.
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