W3000 Datasheet, PDF (9/28 Pages) Agere Systems – W3000 PLL Dual-Band Frequency Synthesizer

Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Serial Data Input
The PLL is programmed via a 3-wire serial bus, utilizing a data pin (DAT), a clock pin (CLK), and a latch pin
(LAT).
Serial Bus Timing Information
DAT
MSB
MSB – 1
LSB
CLK
tCS
tCH
tLL
LAT
OR
LAT
V
t
tCWL
tCWH
tLS
tLWH
Figure 5. Serial Bus Timing Diagram
Table 5. Serial Bus Timing Information
Symbol
Parameter
Min Typ
Max
tCS
Data to Clock Setup Time
33
—
—
tCH
Data to Clock Hold Time
10
—
—
tCWH Clock Pulse Width High
33
—
—
tCWL Clock Pulse Width Low
33
—
—
tLS
Clock Falling Edge to Latch High Setup Time
0
—
—
tLWH Latch Pulse Width
50
—
—
tLL
Latch to Clock Setup Time
33
—
—
fCLK
Clock Input Frequency
—
—
10
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
Lucent Technologies Inc.
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