W3000 Datasheet, PDF (16/28 Pages) Agere Systems – W3000 PLL Dual-Band Frequency Synthesizer

W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet
December 1999
MAIN Register (continued)
Table 21. M1:M11: Programmable Main Counter Divide Ratio (Bits 9 to 19)
M11 M10 M9 M8 M7 M6 M5 M4 M3 M2
Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
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0
0
0
1
1
1
1
1
1
1
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1
1
1
1
1
1
1
1
1
1
M1
Bit 9
0
1
.
.
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1
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1
Divide
Ratio
M
2
3
.
.
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255
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2047
The main counter divides the frequency of the prescaler output signal and sources the divided signal to the
phase comparator.
Table 22. EN2: Synthesizer Enable (Bit 22)
PWRDN EN2
H
0
H
1
L
0
L
1
Mode
Powerdown
Enable
Powerdown
Powerdown
The REF register also contains an enable bit, EN1 (see Table 16). The W3000 is enabled or powered down with
either the REF or MAIN register, whichever was programmed more recently. The contents of the MAIN and REF
registers are maintained in powerdown mode, providing supply voltages are maintained.
Table 23. B: Band Select (Bit 23)
B
Band
0
Band 1
1
Band 2
In dual-band operation, this bit allows the use of one loop filter by setting the charge pump current to correspond
to the frequency of the band selected. See Table 12 for the available charge pump current settings.
16
Lucent Technologies Inc.