W3000 Datasheet, PDF (15/28 Pages) Agere Systems – W3000 PLL Dual-Band Frequency Synthesizer

Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
MAIN Register
The MAIN register is intended for programming that can occur frequently for dynamic channel switching and
putting the W3000 into power-saving mode.
Table 18. MAIN Register Bit Description (C0 = 0, C1 = 0)
Bit
Name
Description
1
C0 = 0
Register address bit. C0 = 0 for MAIN (last bit in serial sequence).
2:8
A[1:7]
Swallow counter for prescaler modulus control.
9:19
M[1:11]
Main counter.
20
Reserved
—
21
Reserved
—
22
EN2
Enable all PLL circuits (0 = powerdown mode).
23
B
Band select for charge pump current control (band 1 = 0, band 2 = 1).
24
C1 = 0
Secondary address bit.
Table 19. MAIN Register
Last bit in serial sequence
First bit in serial sequence
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C0 A A A A A A A M M M M M M M M M M M X X EN B C1
= 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11
=0
Note: X bits are don’t care bits.
Table 20. A1:A7: Swallow Counter Count (Bits 2 to 8)
A7
Bit 8
0
0
0
.
.
.
0
.
.
.
1
A6
Bit 7
0
0
0
.
.
.
1
.
.
.
1
A5
Bit 6
0
0
0
.
.
.
1
.
.
.
1
A4
Bit 5
0
0
0
.
.
.
1
.
.
.
1
A3
Bit 4
0
0
0
.
.
.
1
.
.
.
1
A2
Bit 3
0
0
1
.
.
.
1
.
.
.
1
A1
Bit 2
0
1
0
.
.
.
1
.
.
.
1
Counter Ratio
0
1
2
.
.
.
63
.
.
.
127
Lucent Technologies Inc.
15