ADV7341_15 Datasheet, PDF (97/108 Pages) Analog Devices – Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS

Data Sheet
Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x02
0x10 RGB output enabled. RGB output sync
enabled.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x10 10-bit input enabled.
Table 68. 10-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x02
0x10 RGB output enabled. RGB output sync
enabled.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x10 10-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 69. 20-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x18 20-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
ADV7340/ADV7341
Table 70. 20-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset
0x00
0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x02
0x10 RGB output enabled. RGB output sync
enabled.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x18 20-bit input enabled.
0x8A
0x0C Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 71. 30-Bit 525i RGB In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x87
0x80 RGB input enabled.
0x88
0x10 10-bit input enabled (10 × 3 = 30-bit).
0x8A
0x0C Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 72. 30-Bit 525i RGB In, RGB and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x02
0x10 RGB output enabled. RGB output sync
enabled.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x87
0x80 RGB input enabled.
0x88
0x10 10-bit input enabled (10 × 3 = 30-bit).
0x8A
0x0C Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Rev. C | Page 97 of 108