ADV7341_15 Datasheet, PDF (35/108 Pages) Analog Devices – Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS

Data Sheet
ADV7340/ADV7341
Table 21. Register 0x30
SR7 to
SR0 Register
0x30
ED/HD Mode
Register 1
Bit Description
ED/HD output
standard
ED/HD input
synchronization
format
ED/HD standard²
Bit Number
7 6 5 4 3 2 1 0 Register Setting
0 0 EIA770.2 output,
EIA770.3 output
0 1 EIA770.1 output
1 0 Output levels for full
input range
1 1 Reserved
0
External HSYNC, VSYNC
and field inputs¹
1
Embedded EAV/SAV
codes
00000
SMPTE 293M,
ITU-BT.1358
00010
BTA-1004, ITU-BT.1362
00011
ITU-BT.1358
00100
ITU-BT.1362
00101
SMPTE 296M-1,
SMPTE 274M-2
00110
SMPTE 296M-3
00111
SMPTE 296M-4,
SMPTE 274M-5
01000
SMPTE 296M-6.
01001
SMPTE 296M-7,
SMPTE 296M-8
01010
SMPTE 240M
01011
Reserved
01100
Reserved
01101
SMPTE 274M-4,
SMPTE 274M-5
01110
SMPTE 274M-6
01111
SMPTE 274M-7,
SMPTE 274M-8
10000
SMPTE 274M-9
10001
SMPTE 274M-10,
SMPTE 274M-11
10010
ITU-R BT.709-5
10011–11111
Reserved
Note
ED
HD
Reset
Value
0x00
525p at 59.94 Hz
525p at 59.94 Hz
625p at 50 Hz
625p at 50 Hz
720p at 60/59.94 Hz
720p at 50 Hz
720p at 30/29.97 Hz
720p at 25 Hz
720p at 24/23.98 Hz
1035i at 60/59.94 Hz
1080i at 30/29.97 Hz
1080i at 25 Hz
1080p at 30/29.97 Hz
1080p at 25 Hz
1080p at 24/23.98 Hz
1080Psf at 24 Hz
1 _{Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6.}
2 _{See the HD Interlace External P_HSYNC and P_VSYNC Considerations section for more information.}
Rev. C | Page 35 of 108