ADV7341_15 Datasheet, PDF (18/108 Pages) Analog Devices – Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS

ADV7340/ADV7341
Data Sheet
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y9 TO Y2/
Y9 TO Y0
Cb0 Y0 Cr0 Y1
b
a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 15. ED-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. C | Page 18 of 108