ADV7341_15 Datasheet, PDF (96/108 Pages) Analog Devices – Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS

ADV7340/ADV7341
Data Sheet
CONFIGURATION SCRIPTS
The scripts listed in the following pages can be used to configure the ADV7340/ ADV7341 for basic operation. Certain features are
enabled by default. If required for a specific application, additional features can be enabled. Table 64 lists the scripts available for SD
modes of operation. Similarly, Table 85 and Table 112 list the scripts available for ED and HD modes of operation, respectively. For all
scripts, only the necessary register writes are included. All other registers are assumed to have their default values.
STANDARD DEFINITION
Table 64. SD Configuration Scripts
Input Format Input Data Width¹
525i (NTSC)
525i (NTSC)
10-bit SDR
10-bit SDR
525i (NTSC)
10-bit SDR
525i (NTSC)
10-bit SDR
525i (NTSC)
20-bit SDR
525i (NTSC)
20-bit SDR
525i (NTSC)
30-bit SDR
525i (NTSC)
30-bit SDR
NTSC Sq. Pixel 10-bit SDR
NTSC Sq. Pixel 30-bit SDR
625i (PAL)
10-bit SDR
625i (PAL)
10-bit SDR
625i (PAL)
10-bit SDR
625i (PAL)
10-bit SDR
625i (PAL)
20-bit SDR
625i (PAL)
20-bit SDR
625i (PAL)
30-bit SDR
625i (PAL)
30-bit SDR
PAL Sq. Pixel 10-bit SDR
PAL Sq. Pixel 30-bit SDR
Synchronization Format
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
YCrCb
RGB
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
YCrCb
RGB
Output Color Space
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
Table Number
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
1 _{SDR = single data rate.}
Table 65. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb and
CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x10 10-bit input enabled.
Table 66. 10-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0xFC All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x10 10-bit input enabled.
0x8A
0x0C Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Rev. C | Page 96 of 108