AD9927_15 Datasheet, PDF (95/100 Pages) Analog Devices – 14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

AD9927
Table 60. V-Sequence (VSEQ) Registers
Data Default Update
Address Bits Value Type Name
00
[0]
X
SCP
CLPOBPOL
[1]
X
PBLKPOL
[5:2] X
HOLD
[9:6] X
VMASK_EN
[13:10] X
CONCAT_GRP
[15:14] X
VREP_MODE
[19:16] X
[23:20] X
[25:24] X
LASTREPLEN_EN
LASTTOG_EN
HBLK_MODE
01
[12:0] X
SCP
HDLENE
[25:13] X
HDLENO
02
[23:0] X
SCP
VSGPATSEL
[24]
[25]
03
[23:0] X
04
[23:0] X
05
[23:0] X
06
[23:0] X
07
[23:0] X
08
[23:0] X
09
[4:0] X
[9:5] X
[14:10] X
[19:15] X
0A
[12:0] X
[25:13] X
0B
[12:0] X
[25:13] X
0C
[12:0] X
[25:13] X
0D
[12:0] X
[25:13] X
0E
[12:0] X
[25:13] X
HDLENE_13
HDLENO_13
SCP
VPOL_A
SCP
VPOL_B
SCP
VPOL_C
SCP
VPOL_D
SCP
GROUPSEL_0
SCP
GROUPSEL_1
SCP
VPATSELA
VPATSELB
VPATSELC
VPATSELD
SCP
VSTARTA
VLENA
SCP
VREPA_1
VREPA_2
SCP
VREPA_3
VREPA_4
SCP
VSTARTB
VLENB
SCP
VREPB_ODD
VREPB_EVEN
Description
CLPOB start polarity.
PBLK start polarity.
1 = enable HOLD function for each VPAT group (A, B, C, D).
1 = enable FREEZE/RESUME for each VPAT group (A, B, C, D).
Combine multiple VPAT groups together in one sequence. Set register
equal to 0x01 to enable.
Defines V-alternation repetition mode.
00 = single pattern alternation for all groups.
01 = two pattern alternation for all groups.
10 = three-pattern alternation for Group A. Groups B, C, and D
follow pattern {0, 1, 1, 0, 1, 1…}.
11 = four-pattern alternation for Group A. Two-pattern alternation
for Groups B, C, and D.
Enable use of last repetition counter for last repetition length of each group.
Enable the fifth toggle position for all V-signals in each group.
Selection of HBLK modes.
00 = HBLK Mode 0 (normal six-toggle operation).
01 = HBLK Mode 1.
10 = HBLK Mode 2. (Address 0x19 to Address 0x1E operate differently.)
11 = test only, do not access.
HD line length for even lines.
HD line length for odd lines.
Selects which two toggle positions are used by each V-output when they
are configured as VSG pulses (Miscellaneous Register Address 0x1C, fixed
register area).
0 = use Toggles 1, 2; 1 = use Toggles 3, 4.
HD length Bit [13] for even lines when 14-bit H-counter is enabled.
HD length Bit [13] for odd lines when 14-bit H-counter is enabled.
Starting polarities for each V-output signal (Group A).
Starting polarities for each V-output signal (Group B).
Starting polarities for each V-output signal (Group C).
Starting polarities for each V-output signal (Group D).
Select which group each XV1 ~ XV12 signal is assigned to.
00 = Group A, 01 = Group B, 10 = Group C, 11 = Group D.
[1:0]: XV1; [3:2]: XV2 … [23:22]: XV12.
Select which group each XV13 ~ XV24 signal is assigned to.
00 = Group A, 01 = Group B, 10 = Group C, 11 = Group D.
[1:0]: XV13; [3:2]: XV14 … [23:22]: XV24.
Selected VPAT group for Group A, from VPAT Group 0 ~ 31.
Selected VPAT group for Group B, from VPAT Group 0 ~ 31.
Selected VPAT group for Group C, from VPAT Group 0 ~ 31.
Selected VPAT group for Group D, from VPAT Group 0 ~ 31.
Start position of selected V-Pattern Group A.
Length of selected V-Pattern Group A.
Number of repetitions for V-Pattern Group A for first lines.
Number of repetitions for V-Pattern Group A for second lines.
Number of repetitions for V-Pattern Group A for third lines.
Number of repetitions for V-Pattern Group A for fourth lines.
Start position of selected V-Pattern Group B.
Length of selected V-Pattern Group B.
Number of repetitions for V-Pattern Group B for odd lines.
Number of repetitions for V-Pattern Group B for even lines.
Rev. 0 | Page 95 of 100