AD9927_15 Datasheet, PDF (29/100 Pages) Analog Devices – 14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

1
CREATE THE VERTICAL PATTERN GROUPS,
UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.
XV1
XV2
XV3
VPAT0
XV23
XV24
XV1
XV2
XV3
VPAT1
XV23
XV24
AD9927
2
BUILD THE V-SEQUENCES BY ADDING START POLARITY,
LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,
GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.
XV1
XV2
V-SEQUENCE 0
XV3
(VPAT0, 1 REP)
XV23
XV24
XV1
XV2
V-SEQUENCE 1
XV3
(VPAT1, 2 REP)
XV23
XV24
XV1
XV2
V-SEQUENCE 2
XV3
(VPAT1, N REP)
XV23
XV24
USE THE MODE REGISTERS TO CONTROL WHICH FIELDS
4 ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN
FIELDS MAY BE COMBINED IN ANY ORDER).
FIELD0
FIELD1
FIELD2
FIELD3
FIELD4
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS
3 AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF NINE REGIONS IN EACH FIELD).
FIELD 0
REGION 0: USE V-SEQUENCE 2
REGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 0
REGION 0: USE V-SEQUENCE 3
REGIORNE2G:IUOSNE1V: U-SSEEQVU-ESNECQEUE3NCE 2
REGION 1: USE V-SEQUENCE 2
FIELD5
FIELD1
FIELD4
FIELD2
REGION 3: USE V-SEQUENCE 0
REGION 2: USE V-SEQUENCE 1
REGION 2: USE V-SEQUENCE 1
REGION 4: USE V-SEQUENCE 2
FIELD1
FIELD2
Figure 34. Summary of Vertical Timing Generation
Rev. 0 | Page 29 of 100