AD9927_15 Datasheet, PDF (53/100 Pages) Analog Devices – 14-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

VERTICAL TIMING EXAMPLE
To better understand how the AD9927 vertical timing
generation is used, consider the example CCD timing chart in
Figure 68. This example illustrates a CCD using a general
3-field readout technique. As described in the previous field
section, each readout field must be divided into separate regions
to perform each step of the readout. The sequence change
positions (SCP) determine the line boundaries for each region,
and the SEQx registers assign a particular V-sequence to each
region. The V-sequences contain the specific timing
information required in each region: V1 to V6 pulses (using V-
pattern groups), HBLK/CLPOB timing, and VSG patterns for
the SG active lines.
This timing example requires four regions for each of the three
fields, labeled Region 0, Region 1, Region 2, and Region 3.
Because the AD9927 allows many individual fields to be pro-
grammed, FIELD0, FIELD1, and FIELD2 can be used to meet
the requirements of this timing example. The four regions for
each field are very similar in this example, but the individual
registers for each field allow flexibility to accommodate other
timing charts.
Region 0 is a high speed, vertical shift region. Sweep mode can
be used to generate this timing operation with the desired
number of high speed vertical pulses needed to clear any charge
from the CCD’s vertical registers.
AD9927
Region 1 consists of only two lines and uses standard single-
line, vertical shift timing. The timing of this region area is the
same as the timing in Region 3.
Region 2 is the sensor gate line where the VSG pulses transfer
the image into the vertical CCD registers. This region might
require the use of the second V-pattern group for the SG
active line.
Region 3 also uses the standard single-line, vertical shift timing,
the same timing as Region 1. Four regions are required in each
of the three fields.
The timing for Region 1 and Region 3 is essentially the same,
reducing the complexity of the register programming. Other
registers need to be used during the actual readout operation.
These include the MODE registers, shutter control registers
(PRIMARY_ACTION, SUBCK, GPO for MSHUT, and VSUB
control) and AFE gain register.
Important Note Regarding Signal Polarities
When programming the AD9927 to generate the V1 to V24 and
SUBCK signals, the external V-driver circuit usually inverts
these signals. Carefully check the required timing signals needed
at the input and the output of the V-driver circuit being used and
adjust the polarities of the AD9927 outputs accordingly.
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