MT-022 Datasheet, PDF (9/12 Pages) Analog Devices – ADC Architectures III: Sigma-Delta ADC Basics

MT-022
By using more than one integration and summing stage in the Σ-Δ modulator, we can achieve
higher orders of quantization noise shaping and even better ENOB for a given oversampling ratio
as is shown in Figure 7 for both a first and second-order Σ-Δ modulator.
2ND ORDER
DIGITAL
FILTER
1ST ORDER
f_s
2
Kf_s
2
Figure 7: Sigma-Delta Modulators Shape Quantization Noise
The block diagram for the second-order Σ-Δ modulator is shown in Figure 8. Third, and higher,
order Σ-Δ ADCs were once thought to be potentially unstable at some values of input—recent
analyses using finite rather than infinite gains in the comparator have shown that this is not
necessarily so, but even if instability does start to occur, the DSP in the digital filter and
decimator can be made to recognize incipient instability and react to prevent it.
V_{IN +}
∑
_
INTEGRATOR
∫
+_∑
_
INTEGRATOR
CLOCK
Kf_s
∫
+
_
1-BIT
DAC
1-BIT
DATA
STREAM
DIGITAL FILTER
AND
DECIMATOR
N-BITS
f_s
Figure 8: Second-Order Sigma-Delta ADC
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