MT-022 Datasheet, PDF(6/12 Page) Analog Devices – ADC Architectures III: Sigma-Delta ADC Basics

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MT-022 Datasheet, PDF (6/12 Pages) Analog Devices – ADC Architectures III: Sigma-Delta ADC Basics

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MT-022

VIN

+â

INTEGRATOR

â«A

CLOCK

Kfs

LATCHED

COMPARATOR

(1-BIT ADC)

+VREF

1-BIT

DAC

1-BIT DATA

STREAM

âVREF

SIGMA-DELTA MODULATOR

DIGITAL

FILTER

AND

DECIMATOR

N-BITS

1-BIT,

Kfs

Figure 4: First-Order Sigma-Delta ADC

Intuitively, a Î£-Î ADC operates as follows. Assume a dc input at VIN. The integrator is

constantly ramping up or down at node A. The output of the comparator is fed back through a 1-

bit DAC to the summing input at node B. The negative feedback loop from the comparator

output through the 1-bit DAC back to the summing point will force the average dc voltage at

node B to be equal to VIN. This implies that the average DAC output voltage must equal the

input voltage VIN. The average DAC output voltage is controlled by the ones-density in the 1-bit

data stream from the comparator output. As the input signal increases towards +VREF, the number

of "ones" in the serial bit stream increases, and the number of "zeros" decreases. Similarly, as the

signal goes negative towards âVREF, the number of "ones" in the serial bit stream decreases, and

the number of "zeros" increases. From a very simplistic standpoint, this analysis shows that the

average value of the input voltage is contained in the serial bit stream out of the comparator. The

digital filter and decimator process the serial bit stream and produce the final output data.

For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually

meaningless. Only when a large number of samples are averaged, will a meaningful value result.

The Î£-Î modulator is very difficult to analyze in the time domain because of this apparent

randomness of the single-bit data output. If the input signal is near positive full-scale, it is clear

that there will be more "1"s than "0"s in the bit stream. Likewise, for signals near negative full-

scale, there will be more "0"s than "1"s in the bit stream. For signals near midscale, there will be

approximately an equal number of "1"s and "0"s. Figure 5 shows the output of the integrator for

two input conditions. The first is for an input of zero (midscale). To decode the output, pass the

output samples through a simple digital lowpass filter that averages every four samples. The

output of the filter is 2/4. This value represents bipolar zero. If more samples are averaged,

more dynamic range is achieved. For example, averaging 4 samples gives 2 bits of resolution,

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