MT-022 Datasheet, PDF (7/12 Pages) Analog Devices – ADC Architectures III: Sigma-Delta ADC Basics

MT-022
while averaging 8 samples yields 4/8, or 3 bits of resolution. In the bottom waveform of Figure
5, the average obtained for 4 samples is 3/4, and the average for 8 samples is 6/8.
Figure 5: Sigma-Delta Modulator Waveforms
For an interactive tutorial on the time domain characteristics of the Σ-Δ modulator, refer to the
Sigma-Delta Tutorial located in the Analog Devices' Design Center which gives a graphical
illustration of the behavior of an idealized Σ-Δ ADC.
The Σ-Δ ADC can also be viewed as a synchronous voltage-to-frequency converter followed by
a counter. If the number of "1"s in the output data stream is counted over a sufficient number of
samples, the counter output will represent the digital value of the input. Obviously, this method
of averaging will only work for dc or very slowly changing input signals. In addition, 2^N clock
cycles must be counted in order to achieve N-bit effective resolution, thereby severely limiting
the effective sampling rate.
It should be noted that because the digital filter is an integral part of the Σ-Δ ADC, there is a
built-in "pipeline" delay (sometimes called "latency") primarily determined by the number of
taps in the digital filter. Digital filters in Σ-Δ ADCs can be quite large (several hundred taps), so
the latency may become an issue in multiplexed applications where the appropriate amount of
settling time must be allowed after switching channels.
FREQUENCY DOMAIN ANALYSIS OF A SIGMA-DELTA ADC AND NOISE
SHAPING
Further time-domain analysis is not productive, and the concept of noise shaping is best
explained in the frequency domain by considering the simple Σ-Δ modulator model in Figure 6.
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