DAC8426 Datasheet, PDF (9/12 Pages) Analog Devices – Quad 8-Bit Voltage Out CMOS DAC Complete with Internal 10 V Reference

DAC8426
APPLICATIONS SETUP
UNIPOLAR OUTPUT OPERATION
The output voltage appearing at any output V_OUT is equal to the
internal 10 V reference multiplied by the decimal value of the
latched digital input divided by 2⁸ (= 256). In equation form:
V_OUT(D) = D/256 × 10 V
where D = 0₁₀ to 255₁₀
Figure 4. Amplifier Output Stage
Note that the maximum possible output is 1 LSB less than the
internal 10 V reference, that is, 255/256 × 10 V = 9.961 V.
Table II lists output voltages for a given digital input. The total
unadjusted error (TUE) specification of the product grade used
determines the output tolerances of the values listed in Table II.
For example, a ± 2 LSB grade DAC8426FP loaded with decimal
128₁₀ (half-scale) would have a guaranteed output voltage oc-
curring in the range of 5 V ± 2 LSB, which is 5 V ± (2 × 10 V/256)
= 5 V ± 0.078 V. Therefore V_OUT is guaranteed to occur in the
following range:
4.922 V ≤ V_OUT(128) ≤ 5.078 V
One additional characteristic guaranteed is a DNL of ± 1 LSB
on all grades. The DAC8426 is therefore guaranteed to be mon-
otonic. In the situation where a continuously positive 1 LSB
digital increment is applied, the output voltage will always in-
crease in value, never decrease. This is very important is servo
applications and other closed-loop feedback systems. Finally, in
the typical characteristic curves, long term output voltage drift
(stability) is provided.
BIPOLAR OUTPUT OPERATION
An external op amp plus two resistors can easily convert any
DAC output to bipolar output voltage swings. Figure 6 shows all
four DACs output operating in bipolar mode. This is the general
expression describing the bipolar output transfer equation:
V_OUT(D) = [(1 +R₂/R₁) × D/256 × 10 V] –R₂/R₁ × 10 V,
where D = 0₁₀ to 255₁₀
If R₁ = R₂, then V_OUT becomes:
V_OUT (D) = (D/128–1) × 10 V
Table III lists various output voltages with R₁ = R₂ versus digital
input code. This coding is considered offset binary. Note that
the LSB step size is now 20 V/256 = 0.078 V, twice as large as
the unipolar output case previously discussed. In order to minimize
gain and offset errors, choose R₁ and R₂ to match and track
within 0.1% over the selected operating temperature range
of interest.
Table II. Unipolar Output Voltage as a Function of
Digital Input Code
Digital Input
Code
Analog Output
Voltage (= D/256 × 10 V)
255
9.961 V
Full-Scale (FS)
254
9.922 V
FS-1 LSB
129
5.039 V
128
5.000 V
Half-Scale
127
4.961 V
1
0.039 V
1 LSB
0
0.000 V
Zero-Scale
Figure 5. DAC Output Current Sink
For the top grade DAC8426EP ± 1 LSB total unadjusted error
(TUE), the guaranteed range is 4.961 V ≤ V_OUT (128₁₀) ≤ 5.039 V.
These tolerances provide the worst case analysis including tem-
perature changes.
OFFSETTING AGND
Since the DAC ladder and bandgap reference are terminated at
AGND, it is possible to offset AGND positive with respect to
DGND. The 10 V output span remains if a positive offset is ap-
plied to AGND. The offset voltage source connected to AGND
must be capable of sinking 14 mA. AGND cannot be taken
negative with respect to DGND; this would forward bias an in-
ternal diode. Allowance must be made at V_DD to maintain 3.5 V
of headroom above V_REFOUT. This connection setup is useful
in single supply applications where virtual ground needs to be
slightly positive with respect to ground. In this application con-
nect V_SS to DGND to take advantage of the extra buffer output
current sinking capability when the DAC output is programmed
to all zeros code, see Figure 7.
REV. C
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