AD9652_17 Datasheet, PDF (9/37 Pages) Analog Devices – Analog-to-Digital Converter (ADC)

AD9652
Timing Diagrams
VIN±x
CLK+
CLK–
DCO–
DCO+
PARALLEL
INTERLEAVED
D0± (LSB)
CHANNEL A
AND
CHANNEL B
D15± (MSB)
Data Sheet
N–1
t_CH
t_A
N
N+1
t_CLK
N+2
N+3
N+4
N+5
t_DCO
t_SKEW
t_PD
CH A CH B
N – 26 N – 26
CH A
N – 25
CH B
N – 25
CH A
N – 24
CH B
N – 24
CH A
N – 23
CH B
N – 23
CH A
N – 22
CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 26 N – 26 N – 25 N – 25 N – 24 N – 24 N – 23 N – 23 N – 22
Figure 2. LVDS Data Output Timing
CLK±
SYNC
t_SSYNC
t_HSYNC
Figure 3. SYNC Timing Inputs
t_DS
t_HIGH
t_CLK
t_H
t_S
t_DH
t_LOW
CSB
SCLK DON’T CARE
DON’T CARE
SDIO DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 4. Serial Port Interface Timing Diagram
Rev. B | Page 8 of 36