AD9652_17 Datasheet, PDF (1/37 Pages) Analog Devices – Analog-to-Digital Converter (ADC)

Data Sheet
16-Bit, 310 MSPS, 3.3 V/1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9652
FEATURES
High dynamic range
SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS)
SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS)
Noise spectral density (NSD) = −156.7 dBFS/Hz input noise
at −1 dBFS at 70 MHz
NSD = −157.6 dBFS/Hz for small signal at −7dBFS at 70 MHz
90 dB channel isolation/crosstalk
On-chip dithering (improves small signal linearity)
Excellent IF sampling performance
SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS)
SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS)
Full power bandwidth of 465 MHz
On-chip 3.3 V buffer
Programmable input span of 2 V p-p to 2.5 V p-p (default)
Differential clock input receiver with 1, 2, 4, and 8 integer
inputs (clock divider input accepts up to 1.24 GHz)
Internal ADC clock duty cycle stabilizer
SYNC input allows multichip synchronization
Total power consumption: 2.16 W
3.3 V and 1.8 V supply voltages
DDR LVDS (ANSI-644 levels) outputs
Serial port control
Energy saving power-down modes
APPLICATIONS
Military radar and communications
Multimode digital receivers (3G or 4G)
Test and instrumentation
Smart antenna systems
GENERAL DESCRIPTION
The AD9652 is a dual, 16-bit analog-to-digital converter (ADC)
with sampling speeds of up to 310 MSPS. It is designed to
support demanding, high speed signal processing applications
that require exceptional dynamic range over a wide input
frequency range (up to 465 MHz). Its exceptional low noise
floor of −157.6 dBFS and large signal spurious-free dynamic
range (SFDR) performance (exceeding 85 dBFS, typical) allows
low level signals to be resolved in the presence of large signals.
The dual ADC cores feature a multistage, pipelined architecture
with integrated output error correction logic. A high performance
on-chip buffer and internal voltage reference simplify the inter-
face to external driving circuitry while preserving the exceptional
performance of the ADC.
The AD9652 can support input clock frequencies of up to
1.24 GHz with a 1, 2, 4, and 8 integer clock divider to generate
the ADC sample clock. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle.
Rev. B
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FUNCTIONAL BLOCK DIAGRAM
AVDD3 AVDD SDIO SCLK CSB
DRVDD
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
SPI
AD9652
PROGRAMMING DATA
ADC
DDR DATA
INTERLEAVER
16
LVDS OUTPUT
DRIVER
REF
SELECT
DIVIDE 1
TO 8
DUTY CYCLE
DCO
STABILIZER GENERATION
ADC
MULTICHIP
SYNC
OR+, OR–
D15± (MSB)
TO
D0± (LSB)*
CLK+
CLK–
DCO+
DCO–
AGND
SYNC
PDWN
*THESE PINS ARE FOR CHANNEL A AND CHANNEL B.
Figure 1.
The 16-bit output data (with an overrange bit) from each ADC
is interleaved onto a single LVDS output port along with a
double data rate (DDR) clock. Programming for setup and control
are accomplished using a 3-wire SPI-compatible serial interface.
The AD9652 is available in a 144-ball CSP_BGA and is
specified over the industrial temperature range of −40°C to
+85°C. This product is protected by pending U.S. patents.
PRODUCT HIGHLIGHTS
1. Integrated dual, 16-bit, 310 MSPS ADCs.
2. On-chip buffer simplifies ADC driver interface.
3. Operation from 3.3 V and 1.8 V supplies and a separate
digital output driver supply accommodating LVDS outputs.
4. Proprietary differential input maintains excellent signal-to-
noise ratio (SNR) performance for input frequencies of up
to 485 MHz.
5. SYNC input allows synchronization of multiple devices.
6. Three-wire, 3.3 V or 1.8 V SPI port for register programming
and readback.
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