AD9652_17 Datasheet, PDF (21/37 Pages) Analog Devices – Analog-to-Digital Converter (ADC)

AD9652
THEORY OF OPERATION
The AD9652 is a dual, 16-bit ADC with sampling speeds of up
to 310 MSPS. The AD9652 is designed to support communications
and instrumentation applications where high performance and
wide bandwidth are desired.
The dual ADC design can be used for diversity receivers, where
the ADCs operate identically on the same carrier but from two
separate antennae. The ADCs can also be operated with
independent analog inputs. The user can sample frequencies
from dc to 310 MHz using appropriate low-pass or band-pass
filtering at the ADC inputs with little loss in ADC performance.
A typical operation of 485 MHz at the analog input is permitted
but occurs at the expense of increased ADC noise and distortion.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9652 are accomplished
using a 3-wire, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9652 consists of a dual, buffered front-end sample-and-
hold circuit, followed by a pipelined switched-capacitor ADC.
The AD9652 uses a unique architecture that utilizes the benefits
of pipelined converters, as well as a novel input circuit to
maximize performance of the first stage.
The quantized outputs from each stage are combined to produce a
16-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residual multiplying
DAC (MDAC). The MDAC magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each
stage to facilitate digital correction of flash errors. The last stage
consists of a flash ADC.
The AD9652 uses internal digital processing to continually
track internal errors that occur at each of the pipeline stages and
corrects for them to ensure continuous performance over
various operating conditions. This requires additional start-up
time due to the resetting and collection of correction data.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-
ended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing digital
output noise to be separated from the analog core. During power-
down, the output buffers enter a high impedance state.
Data Sheet
ANALOG INPUT CONSIDERATIONS
The analog inputs to the AD9652 are high performance
differential buffers that are designed for optimum performance
while processing a differential input signal. The input buffer
provides a consistent input impedance to ease interface of the
analog input.
The differential analog input impedance is approximately 54 kΩ
in parallel with a 5.8 pF capacitor. A passive network of discrete
components can create a low-pass filter at the ADC input; the
precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications,
reduce the shunt capacitors. In combination with the driving
source impedance, the shunt capacitors limit the input bandwidth.
Refer to the Analog Dialogue article, “Transformer-Coupled
Front-End for Wideband A/D Converters,” for more information
on this subject.
The AD9652 uses internal optimized settings for the various
input signal frequencies. Register 0x22A configures the ADC
for the desired frequency band.
Table 9. Register 0x22A Settings
Register 0x22A Setting Input Frequency Range
0 (Default)
0 to 155 MHz (1^st Nyquist)
1
155 to 310 MHz (2^nd Nyquist)
2
310 MHz and above (3^rd Nyquist)
For best dynamic performance, the source impedances driving
each of the differential inputs, match VIN±x, and differentially
balance the inputs.
Input Common Mode
The analog inputs of the AD9652 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that the common-mode voltage
equals 2.0 V is recommended for optimum performance. An
on-board common-mode voltage reference is included in the
design and is available from the VCM pin. Using the VCM
output to set the input common mode is recommended. The
VCM pin must be decoupled to ground with a 0.1 μF capacitor,
as described in the Applications Information section. Place this
decoupling capacitor close to the pin to minimize the series
resistance and inductance between the device and this capacitor.
Common-Mode Voltage Servo
In applications where there may be a voltage loss between the VCM
output of the AD9652 and the analog inputs, the common-mode
voltage servo can be enabled. When the inputs are ac-coupled and a
resistance of >100 Ω is placed between the VCM output and the
analog inputs, a significant voltage drop can occur; enable the
common-mode voltage servo. Setting Bit 0 in Register 0x0F to a
logic high enables the VCM servo mode.
Rev. B | Page 20 of 36