AD9652_17 Datasheet, PDF (25/37 Pages) Analog Devices – Analog-to-Digital Converter (ADC)

AD9652
Data Sheet
Clock Input Options
The AD9652 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 63. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516-5,
AD9517-1, AD9518-1, AD9520-5, AD9522-1, AD9523, and
AD9524 clock drivers offer excellent jitter performance.
Figure 60 and Figure 61 show two preferable methods for
clocking the AD9652 (at clock rates of up to 1240 MHz). A low
jitter clock source is converted from a single-ended signal to a
differential signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 1240 MHz, and the RF
transformer is recommended for clock frequencies from
80 MHz to 200 MHz. The back-to-back Schottky diodes are
used across the transformer secondary or the balun balanced
side to limit clock amplitude excursions into the AD9652 to
approximately 0.8 V p-p differential. This limit helps prevent
large voltage swings of the clock from feeding through to other
portions of the AD9652, while preserving fast rise and fall times
of the clock, which are critical to low jitter performance.
CLOCK
INPUT
390pF
Mini-Circuits^®
ADT1-1WT, 1:1Z
XFMR ^390pF
50Ω ^100Ω
390pF
SCHOTTKY
DIODES:
HSMS2822
ADC
CLK+
CLK–
Figure 60. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
CLOCK
INPUT
50kΩ
0.1µF
AD95xx
0.1µF ^{LVDS DRIVER}
50kΩ
0.1µF
100Ω
0.1µF
ADC
CLK+
CLK–
Figure 63. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD9652 contains an input clock divider with the ability to
divide the input clock by integer values of 1, 2, 4 or 8. In these
cases, the DCS is enabled by default on power-up. The clock
divide ratio is set in Register 0x0B.
The AD9652 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple devices to have
their clock dividers aligned to guarantee simultaneous input
sampling. With the divider enabled and the SYNC option used,
the ADC clock divider output phase can be adjusted after
synchronization in increments of input clock cycles using
Register 0x16.
390pF
CLOCK
INPUT
25Ω
390pF
ADC
CLK+
390pF
1nF
CLK–
25Ω
SCHOTTKY
DIODES:
HSMS2822
Figure 61. Balun-Coupled Differential Clock (Up to 1240 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins as shown in Figure 62. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516-5, AD9517-1, AD9518-1,
AD9520-5, AD9522-1, AD9523, AD9524, and ADCLK905/
ADCLK907/ADCLK925 clock drivers offer excellent jitter
performance.
CLOCK
INPUT
CLOCK
INPUT
50kΩ
0.1µF
AD95xx
0.1µF ^{PECL DRIVER}
50kΩ
240Ω
0.1µF
ADC
CLK+
0.1µF
240Ω
100Ω
CLK–
Figure 62. Differential PECL Sample Clock (Up to 1240 MHz)
Drive the SYNC input using a single-ended CMOS type signal.
If not used, connect the SYNC pin to ground.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9652 contains a clock DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD9652.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The
DCS control loop does not function for clock rates less than
80 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate changes
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input clock. During that time period, the
loop is not locked, the DCS loop is bypassed, and internal
Rev. B | Page 24 of 36