AD9600ABCPZ-150 Datasheet, PDF (9/72 Pages) Analog Devices – 10-Bit, 105 MSPS/125 MSPS/150 MSPS

AD9600
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled
DCS Disabled
CLK Period (tCLK)
CLK Pulse Width High
Divide-by-1 Mode,
DCS Enabled
Divide-by-1 Mode,
DCS Disabled
Divide-by-2 Mode,
DCS Enabled
Divide-by-3 Through Divide-
by-8 Modes, DCS Enabled
DATA OUTPUT PARAMETERS
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)¹
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)¹
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)¹
DCO Propagation Delay (tDCO)
CMOS Mode Pipeline Delay
(Latency)
LVDS Mode Pipeline Delay
(Latency) Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time²
OUT-OF-RANGE RECOVERY TIME
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9600ABCPZ-105/
AD9600BCPZ-105
AD9600ABCPZ-125/
AD9600BCPZ-125
AD9600ABCPZ-150/
AD9600BCPZ-150
Min Typ
Max Min Typ
Max Min Typ
Max Unit
625
625
625 MHz
20
105 20
10
105 10
9.5
8
125 20
125 10
6.66
150 MSPS
150 MSPS
ns
2.85 4.75
4.28 4.75
1.6
0.8
6.65 2.4 4
5.23 3.6 4
1.6
0.8
5.6 2.0 3.33
4.4 3.0 3.33
1.6
0.8
4.66 ns
3.66 ns
ns
ns
2.2 4.5
3.8 5.0
5.25
4.25
6.4 2.2 4.5
6.8 3.8 5.0
4.5
3.5
6.4 2.2 4.5
6.8 3.8 5.0
3.83
2.83
6.4 ns
6.8 ns
ns
ns
2.4 5.2
4.0 5.6
5.25
4.25
6.9 2.4 5.2
7.3 4.0 5.6
4.5
3.5
6.9 2.4 5.2
7.3 4.0 5.6
3.83
2.83
6.9 ns
7.3 ns
ns
ns
3.0 3.7
5.2 6.4
12
4.4 3.0 3.8
7.6 5.0 6.2
12
4.5 3.0 3.8
7.4 4.8 5.9
12
4.5 ns
7.3 ns
Cycles
12/12.5
12/12.5
12/12.5
Cycles
1.0
1.0
1.0
ns
0.1
0.1
0.1
ps rms
350
350
350
μs
2
3
3
Cycles
1 _{Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load.}
2 _{Wake-up time is dependent on the value of the decoupling capacitors.}
Rev. B | Page 9 of 72