AD9600ABCPZ-150 Datasheet, PDF (37/72 Pages) Analog Devices – 10-Bit, 105 MSPS/125 MSPS/150 MSPS

CHANNEL/CHIP SYNCHRONIZATION
The AD9600 has a SYNC input that offers the user flexible
synchronization options for synchronizing the internal blocks.
The clock divider sync feature is useful to guarantee synchronized
sample clocks across multiple ADCs. The signal monitor block can
also be synchronized using the SYNC input, allowing properties of
the input signal to be measured during a specific period. The
input clock divider can be enabled to synchronize on a single
occurrence of the sync signal or on every occurrence. The signal
monitor block is synchronized on every SYNC input signal.
AD9600
The SYNC input is internally synchronized to the sample clock;
however, to ensure there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally
synchronized to the input clock signal, meeting the setup and
hold times shown in Table 5. The SYNC input should be driven
using a single-ended CMOS-type signal.
Rev. B | Page 37 of 72