AD9600ABCPZ-150 Datasheet, PDF (49/72 Pages) Analog Devices – 10-Bit, 105 MSPS/125 MSPS/150 MSPS

DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings, or
modes, allowed on the AD9600 evaluation board.
POWER
Connect the switching power supply that is provided with the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.
VIN
The evaluation board is set up for a double-balun configur-
ation analog input with an optimum 50 Ω impedance matching
from 70 MHz to 200 MHz. For more bandwidth response, the
differential capacitor across the analog inputs can be changed or
removed (see Table 10). The common mode of the analog inputs is
developed from the center tap of the transformer via the CML
pin of the ADC (see the Analog Input Considerations section).
VREF
VREF is set to 1.0 V by tying the SENSE pin to ground and
adding a jumper on Header J5 (Pin 1 to Pin 2). This causes the
ADC to operate in the 2.0 V p-p full-scale range. To place the
ADC in the 1.0 V p-p mode (VREF = 0.5 V), a jumper should
be placed on Header J4. A separate external reference option is
also included on the evaluation board. To use an external reference,
connect Pin 1 of J6 to Pin 2 of J6 and provide an external
reference at TP5. Proper use of the VREF options is detailed in
the Voltage Reference section.
RBIAS
RBIAS requires that a 10 kΩ resistor (R503) be connected to
ground. This pin is used to set the ADC core bias current.
CLOCK
The default clock input circuitry is derived from a simple balun-
coupled circuit using a high bandwidth 1:1 impedance ratio balun
(T5) that adds a very low amount of jitter to the clock path. The
clock input is 50 Ω terminated and ac-coupled to handle single-
ended sine wave inputs. The transformer converts the single-ended
input to a differential signal that is clipped before entering the
ADC clock inputs. When the AD9600 input clock divider is used,
clock frequencies up to 625 MHz can be input into the evaluation
board through Connector S5.
PDWN
To enable the power-down feature, connect J7, shorting the
PDWN pin to AVDD.
AD9600
CSB
The CSB pin is internally pulled up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect Pin 1 of J21 to Pin 2 of J21.
SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets
the data format of the outputs. If the pin is left floating, the pin
is internally pulled down, setting the default data format
condition to offset binary. Connecting Pin 1 of J2 to Pin 2 of J2
sets the format to twos complement. If the SPI port is in serial pin
mode, connecting Pin 2 of J2 to Pin 3 of J2 connects the SCLK
pin to the on-board SPI circuitry (see the Serial Port Interface
(SPI) section).
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin acts
to set the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect Pin 1 of J1 to Pin 2 of J1. If the SPI
port is in serial pin mode, connecting Pin 2 of J1 to Pin 3 of J1
connects the SDIO pin to the on-board SPI circuitry (see the
Serial Port Interface (SPI) section).
ALTERNATIVE CLOCK CONFIGURATIONS
Two clocking options are provided on the AD9600 evaluation
board. The first option is to use the on-board crystal oscillator
(Y1) to provide the clock input to the part. To enable this
crystal, Resistors R8 (0 Ω) and R85 (10 kΩ) should be installed
and Resistors R82 and R30 should be removed.
The second option is to use a differential LVPECL clock to
drive the ADC input using the AD9516-4 (U2). When using
this option, the AD9516-4 charge-pump filter components need
to be populated (see Figure 78). Consult the AD9516-4 data
sheet for more information.
To configure the clock input (from S5) to drive the AD9516
reference input instead of directly driving the ADC, the
following components need to be added, removed, and/or
changed.
1. Remove R32, R33, R99, and R101 in the default clock path.
2. Populate C78 and C79 with 0.001 μF capacitors and R78
and R79 with 0 Ω resistors in the clock path.
Additionally, unused AD9516 outputs (one LVDS and one
LVPECL) are routed to optional Connectors S8 through S11 on
the evaluation board.
Rev. B | Page 49 of 72