AD9511_15 Datasheet, PDF(9/60 Page) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

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AD9511_15 Datasheet, PDF (9/60 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

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CLOCK OUTPUT PHASE NOISE

Table 5.

Parameter

CLK1-TO-LVPECL ADDITIVE PHASE NOISE

CLK1 = 622.08 MHz, OUT = 622.08 MHz

Divide Ratio = 1

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK1 = 622.08 MHz, OUT = 155.52 MHz

Divide Ratio = 4

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK1 = 622.08 MHz, OUT = 38.88 MHz

Divide Ratio = 16

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK1 = 491.52 MHz, OUT = 61.44 MHz

Divide Ratio = 8

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK1 = 491.52 MHz, OUT = 245.76 MHz

Divide Ratio = 2

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK1 = 245.76 MHz, OUT = 61.44 MHz

Divide Ratio = 4

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

AD9511

Min Typ Max Unit

Test Conditions/Comments

Distribution Section only; does not

include PLL or external VCO/VCXO

Input slew rate > 1 V/ns

â125

â132

â140

â148

â153

â154

dBc/Hz

â128

â140

â148

â155

â161

dBc/Hz

â135

â145

â158

â165

â166

dBc/Hz

â131

â142

â153

â160

â165

dBc/Hz

â125

â132

â140

â151

â157

â158

dBc/Hz

â138

â144

â154

â163

â164

â165

dBc/Hz

Rev. A | Page 9 of 60

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