AD9511_15 Datasheet, PDF (23/60 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
CENTER 245.75MHz
30kHz/
SPAN 300kHz
Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz,
FOUT = 245.76 MHz, FPFD = 1.2288 MHz, R = 25, N = 200
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100
CENTER 1.5GHz
250kHz/
SPAN 2.5MHz
Figure 13. PLL Reference Spurs: VCO 1.5 GHz, FPFD = 1 MHz
5.0
4.5
4.0
3.5
PUMP DOWN
3.0
PUMP UP
2.5
2.0
1.5
1.0
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
VOLTAGE ON CP PIN (V)
Figure 14. Charge Pump Output Characteristics @ VCPS = 3.3 V
AD9511
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
CENTER 61.44MHz
30kHz/
SPAN 300kHz
Figure 15. Phase Noise, LVPECL, DIV 4, FVCXO = 245.76 MHz,
FOUT = 61.44 MHz, FPFD = 1.2288 MHz, R = 25, N = 200
–135
–140
–145
–150
–155
–160
–165
–170
0.1
1
10
100
PFD FREQUENCY (MHz)
Figure 16. Phase Noise (Referred to CP Output) vs. PFD Frequency
5.0
4.5
4.0
3.5
PUMP DOWN
3.0
PUMP UP
2.5
2.0
1.5
1.0
0.5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOLTAGE ON CP PIN (V)
Figure 17. Charge Pump Output Characteristics @ VCPS = 5.0 V
Rev. A | Page 23 of 60