AD9511_15 Datasheet, PDF(27/60 Page) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

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AD9511_15 Datasheet, PDF (27/60 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

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PLL WITH EXTERNAL VCO AND BAND-PASS

FILTER FOLLOWED BY CLOCK DISTRIBUTION

An external band-pass filter may be used to try to improve the

phase noise and spurious characteristics of the PLL output. This

option is most appropriate to optimize cost by choosing a less

expensive VCO combined with a moderately priced filter. Note

that the BPF is shown outside of the VCO-to-N divider path,

with the BP filter outputs routed to CLK1. Some power can be

saved by shutting off unused functions, as well as by powering

down any unused clock channels (see the Register Map and

Description section).

REFERENCE

INPUT

VREF

REFIN

FUNCTION

CLK1

AD9511

PFD

STATUS

PLL

REF

CHARGE

PUMP

CLK2

DIVIDE

SERIAL

PORT

DIVIDE

DIVIDE ÎT

LVPECL

LVDS/CMOS

Figure 32. AD9511 with VCO and BPF Filter

LOOP

FILTER

VCO

BPF

CLOCK

OUTPUTS

AD9511

Rev. A | Page 27 of 60

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