AD9511_15 Datasheet, PDF (48/60 Pages) Analog Devices – 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

AD9511
Reg.
Addr.
(Hex)
08
08
08
09
09
09
09
09
09
Bit(s) Name
Description
<5:2> PLL Mux Control
<5>
<4>
<3> <2> MUXOUT—Signal on STATUS Pin
0
0
00
Off (Signal Goes Low) (Default)
0
0
01
Digital Lock Detect (Active High)
0
0
10
N Divider Output
0
0
11
Digital Lock Detect (Active Low)
0
1
00
R Divider Output
0
1
01
Analog Lock Detect (N Channel, Open-Drain)
0
1
10
A Counter Output
0
1
11
Prescaler Output (NCLK)
1
0
00
PFD Up Pulse
1
0
01
PFD Down Pulse
1
0
10
Loss-of-Reference (Active High)
1
0
11
Tri-State
1
1
00
Analog Lock Detect (P Channel, Open-Drain)
1
1
01
Loss-of-Reference or Loss-of-Lock (Inverse of DLD)
(Active High)
1
1
10
Loss-of-Reference or Loss-of-Lock (Inverse of DLD)
(Active Low)
1
1
11
Loss-of-Reference (Active Low)
MUXOUT is the PLL portion of the STATUS output MUX.
<6> Phase-Frequency 0 = Negative (Default), 1 = Positive.
Detector (PFD)
Polarity
<7>
Not Used.
<0> Reset All Counters 0 = Normal (Default), 1 = Reset R, A, and B Counters.
<1> N-Counter Reset 0 = Normal (Default), 1 = Reset A and B Counters.
<2> R-Counter Reset 0 = Normal (Default), 1 = Reset R Counter.
<3>
Not Used.
<6:4> Charge Pump (CP)
Current Setting
<6>
<5>
<4>
ICP (mA)
0
0
0
0.60
0
0
1
1.2
0
1
0
1.8
0
1
1
2.4
1
0
0
3.0
1
0
1
3.6
1
1
0
4.2
1
1
1
4.8
Default = 000b.
These currents assume: CPRSET = 5.1 kΩ.
Actual current can be calculated by: CP_lsb = 3.06/CPRSET.
<7>
Not Used.
Rev. A | Page 48 of 60