EVAL-AD7689EDZ Datasheet, PDF (8/32 Pages) Analog Devices – 16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC

AD7682/AD7689
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter¹
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
Data Write/Read During Conversion
CNV Pulse Width
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV Low to SDO D15 MSB Valid
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Rising Edge
DIN Valid Hold Time from SCK Rising Edge
Symbol
tCONV
tACQ
tCYC
tDATA
tCNVH
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
Typ
1.8
5
10
tDSDO + 2
12
12
5
tEN
tDIS
tCLSCK
10
tSDIN
5
tHDIN
5
1 _{See Figure 2 and Figure 3 for load conditions.}
500µA I_OL
Data Sheet
Max
Unit
3.2
μs
μs
μs
1.2
μs
ns
ns
ns
ns
ns
24
ns
30
ns
38
ns
48
ns
21
ns
27
ns
35
ns
45
ns
50
ns
ns
ns
ns
TO SDO
C_L
50pF
1.4V
500µA I_OH
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
t_DELAY
70% VIO
2V OR VIO – 0.5V¹
0.8V OR 0.5V²
t_DELAY
2V OR VIO – 0.5V¹
0.8V OR 0.5V²
1 _{2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.}
2 _{0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.}
Figure 3. Voltage Levels for Timing
Rev. D | Page 8 of 32