EVAL-AD7689EDZ Datasheet, PDF (26/32 Pages) Analog Devices – 16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC

AD7682/AD7689
Data Sheet
GENERAL TIMING WITHOUT A BUSY INDICATOR
Figure 37 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC),
and read/write spanning conversion (RSC). Note that the gating
item for both CFG and data readback is at the end of conversion
(EOC). At EOC, if CNV is high, the busy indicator is disabled.
As detailed previously in the Digital Interface section, the data
access should occur up to safe data reading/writing time, tDATA.
If the full CFG word was not written to prior to EOC, it is dis-
carded and the current configuration remains. If the conversion
result is not read out fully prior to EOC, it is lost as the ADC
updates SDO with the MSB of the current conversion. For
detailed timing, refer to Figure 40 and Figure 41, which depict
reading/writing spanning conversion with all timing details,
including setup, hold, and SCK.
When CNV is brought low after EOC, SDO is driven from high
impedance to the MSB. Falling SCK edges clock out bits starting
with MSB − 1.
The SCK can idle high or low depending on the clock polarity
(CPOL) and clock phase (CPHA) settings if SPI is used. A simple
solution is to use CPOL = CPHA = 0 as shown in Figure 37 with
SCK idling low.
From power-up, in any read/write mode, the first three conver-
sion results are undefined because a valid CFG does not take
place until the 2^nd EOC; thus two dummy conversions are
required. Also, if the state machine writes the CFG during the
power-up state (RDC shown), the CFG register needs to be
rewritten again at the next phase. Note that the first valid data
occurs in Phase (n + 1) when the CFG register is written during
Phase (n − 1).
POWER
UP
PHASE
t_CYC
t_CONV
EOC
SOC
t_DATA
EOC
CONVERSION
(n – 2) UNDEFINED
ACQUISITION
(n – 1) UNDEFINED
CONVERSION
(n – 1) UNDEFINED
ACQUISITION
(n)
EOC
CONVERSION
(n)
ACQUISITION
(n + 1)
EOC
CONVERSION
(n + 1)
ACQUISITION
(n + 2)
NOTE 1
CNV
DIN
RDC
SDO
SCK
XXX
MSB
XXX
DATA (n – 3)
XXX
1
16
CNV
NOTE 1
CFG (n)
DATA (n – 2)
XXX
1
16
NOTE 2
MSB
XXX
CFG (n + 1)
DATA (n – 1)
XXX
1
16
CFG (n + 2)
MSB
(n)
DATA (n)
1
16
MSB
(n + 1)
DIN
RAC
SDO
SCK
CNV
CFG (n)
DATA (n – 2)
XXX
1
16
NOTE 2
NOTE 1
CFG (n + 1)
DATA (n – 1)
XXX
1
16
CFG (n + 2)
DATA (n)
1
16
CFG (n + 3)
DATA (n + 1)
1
DIN
RSC
SDO
CFG (n)
DATA (n – 2)
XXX
CFG (n)
DATA (n – 2)
XXX
CFG (n + 1)
DATA (n – 1)
XXX
CFG (n + 1)
DATA (n – 1)
XXX
CFG (n + 2)
DATA (n)
CFG (n + 2)
DATA (n)
CFG (n + 3)
DATA (n + 1)
SCK
1
n n+1
16
1
n n+1
16
1
n n+1
16
1
n
NOTE 2
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS
REQUIRED TO RETURN SDO TO HIGH-Z.
Figure 37. General Interface Timing for the AD7682/AD7689 Without a Busy Indicator
Rev. D | Page 26 of 32