EVAL-AD7689EDZ Datasheet, PDF (29/32 Pages) Analog Devices – 16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC

Data Sheet
AD7682/AD7689
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
This mode is used when the AD7682/AD7689 are connected
to any host using an SPI, serial port, or FPGA. The connection
diagram is shown in Figure 40, and the corresponding timing
is given in Figure 41. For the SPI, the host should use CPHA =
CPOL = 0. Reading/writing spanning conversion is shown,
which covers all three modes detailed in the Digital Interface
section. For this mode, the host must generate the data transfer
based on the conversion time. For an interrupt driven transfer
that uses a busy indicator, refer to the Read/Write Spanning
Conversion with a Busy Indicator section.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion irrespec-
tive of the state of CNV. CNV must be returned high before the
safe data transfer time, tDATA, and then held high beyond the
conversion time, tCONV, to avoid generation of the busy signal
indicator.
After the conversion is complete, the AD7682/AD7689 enter
the acquisition phase and power-down. When the host brings
AD7682/
AD7689
CNV
SDO
DIN
SCK
CNV low after tCONV (maximum), the MSB is enabled on SDO.
The host also must enable the MSB of the CFG register at this
time (if necessary) to begin the CFG update. While CNV is low,
both a CFG update and a data readback take place. The first 14
SCK rising edges are used to update the CFG, and the first 15
SCK falling edges clock out the conversion results starting with
MSB − 1. The restriction for both configuring and reading is
that they both must occur before the tDATA time of the next conver-
sion elapses. All 14 bits of CFG[13:0] must be written, or they
are ignored. In addition, if the 16-bit conversion result is not
read back before tDATA elapses, it is lost.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 16^th (or 30^th) SCK falling edge, or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
If CFG readback is enabled, the CFG register associated with the
conversion result is read back MSB first following the LSB of the
conversion result. A total of 30 SCK falling edges is required to
return SDO to high impedance if this is enabled.
DIGITAL HOST
SS
MISO
MOSI
SCK
FOR SPI USE CPHA = 0, CPOL = 0.
Figure 40. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator
CNV
t_DATA
> t_CONV
t_CONV
t_CYC
EOC
RETURN CNV HIGH
FOR NO BUSY
t_ACQ
t_CNVH
t_CONV
t_DATA
EOC
RETURN CNV HIGH
FOR NO BUSY
ACQUISITION
(n - 1)
SCK
DIN
SDO
CONVERSION (n – 1)
t_SCKH
t_SCK
14
t_SCKL
15 ^16/
30
CFG
LSB
X
X
t_EN END CFG (n)
LSB + 1 LSB
(QUIET
TIME)
UPDATE (n)
CFG/SDO
t_CLSCK
t_EN
ACQUISITION (n)
1
2
t_SDIN
t_HDIN
CFG
MSB
CFG
MSB – 1
BEGIN CFG (n + 1)
tt_DHSSDDOO
MSB MSB – 1
CONVERSION (n)
SEE NOTE
14
15
16/
30
(QUIET ACQUISITION
TIME)
(n + 1)
UPDATE (n + 1)
CFG/SDO
CFG
LSB
X
X
t_EN
END CFG (n + 1)
SEE NOTE
LSB + 1 LSB
t_DIS
END DATA (n – 2)
t_DIS
BEGIN DATA (n – 1)
t_DIS
END DATA (n – 1)
t_DIS
NOTES
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
Figure 41. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator
Rev. D | Page 29 of 32