EVAL-AD7689EDZ Datasheet, PDF (25/32 Pages) Analog Devices – 16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC

Data Sheet
AD7682/AD7689
The register can be written to during conversion, during acquisi-
tion, or spanning acquisition/conversion, and is updated at the end
of conversion, tCONV (maximum). There is always a one deep
delay when writing the CFG register. Note that, at power-up, the
CFG register is undefined and two dummy conversions are
required to update the register. To preload the CFG register with a
factory setting, hold DIN high for two conversions. Thus
CFG[13:0] = 0x3FFF. This sets the AD7682/AD7689 for the
following:
13
12
11
10
9
8
7
CFG
INCC
INCC
INCC
INx
INx
INx
• IN[7:0] unipolar referenced to GND, sequenced in order
• Full bandwidth for a one-pole filter
• Internal reference/temperature sensor disabled, buffer
enabled
• Enables the internal sequencer
• No readback of the CFG register
Table 10 summarizes the configuration register bit details. See
the Theory of Operation section for more details.
6
5
4
3
2
1
0
BW
REF
REF
REF
SEQ
SEQ
RB
Table 10. Configuration Register Description
Bit(s) Name Description
[13] CFG Configuration update.
0 = keep current configuration settings.
1 = overwrite contents of register.
[12:10] INCC Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer
to the Input Configurations section.
Bit 12
Bit 11
Bit 10
Function
0
0
X¹
Bipolar differential pairs; INx− referenced to VREF/2 ± 0.1 V.
0
1
0
Bipolar; INx referenced to COM = VREF/2 ± 0.1 V.
0
1
1
Temperature sensor.
1
0
X¹
Unipolar differential pairs; INx− referenced to GND ± 0.1 V.
1
1
0
Unipolar, INx referenced to COM = GND ± 0.1 V.
1
1
1
Unipolar, INx referenced to GND.
[9:7] INx Input channel selection in binary fashion.
AD7682
AD7689
Bit 9
Bit 8
Bit 7
Channel Bit 9
Bit 8
Bit 7
Channel
X¹
0
0
IN0
0
0
0
IN0
X¹
0
1
IN1
0
0
1
IN1
X¹
1
0
IN2
…
…
…
…
X¹
1
1
IN3
1
1
1
IN7
[6]
BW Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section.
0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼.
1 = full BW.
[5:3] REF Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.
Refer to the Voltage Reference Output/Input section.
Bit 5
Bit 4
Bit 3
Function
0
0
0
Internal reference, REF = 2.5 V output, temperature enabled.
0
0
1
Internal reference, REF = 4.096 V output, temperature enabled.
0
1
0
External reference, temperature enabled.
0
1
1
External reference, internal buffer, temperature enabled.
1
1
0
External reference, temperature disabled.
1
1
1
External reference, internal buffer, temperature disabled.
[2:1] SEQ Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Channel Sequencer section.
Bit 2
Bit 1
Function
0
0
Disable sequencer.
0
1
Update configuration during sequence.
1
0
Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.
1
1
Scan IN0 to IN[7:0] (set in CFG[9:7]).
[0]
RB
Read back the CFG register.
0 = read back current configuration at end of data.
1 = do not read back contents of configuration.
1 _{X = don’t care.}
Rev. D | Page 25 of 32