AD7761_17 Datasheet, PDF (72/76 Pages) Analog Devices – 8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW

Data Sheet
AD7761
NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER
Address: 0x14, Reset: 0x00, Name: Negative Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference negative input to each of the ADCs from Channel 0 to Channel 7.
Table 51. Bit Descriptions for Negative Reference Precharge Buffer
Bits
Bit Name
Settings
7
CH7_REFN_BUF
6
CH6_REFN_BUF
5
CH5_REFN_BUF
4
CH4_REFN_BUF
3
CH3_REFN_BUF
2
CH2_REFN_BUF
1
CH1_REFN_BUF
0
CH0_REFN_BUF
Description
0 Off
1 On
0 Off
1 On
0 Off
1 On
0 Off
1 On
0 Off
1 On
0 Off
1 On
0 Off
1 On
0 Off
1 On
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
OFFSET REGISTERS
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_OFFSET_LSB registers are 24 bit, signed twos complement registers for channel
offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital
output by −1/192 LSBs. For example, changing the offset register from 0 to 4800 changes the digital output by −25 LSBs. Because offset
adjustment occurs before gain adjustment, the ratio of 1/192 changes linearly with gain adjustment via the CHx_GAIN_x registers. After a
reset or power cycle, the register values revert to the default factory setting.
Table 52. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, Mid, and LSB
Address
Reset
MSB Mid LSB Name
Description
MSB Mid LSB
0x1E 0x1F 0x20 Channel 0 offset Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00
0x21 0x22 0x23 Channel 1 offset Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00
0x24 0x25 0x26 Channel 2 offset Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00
0x27 0x28 0x29 Channel 3 offset Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00
0x2A 0x2B 0x2C Channel 4 offset Channel 4 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00
0x2D 0x2E 0x2F Channel 5 offset Channel 5 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00
0x30 0x31 0x32 Channel 6 offset Channel 6 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00
0x33 0x34 0x35 Channel 7 offset Channel 7 offset registers: upper, middle, and lower bytes (24 bits in total) 0x00 0x00 0x00
Access
RW
RW
RW
RW
RW
RW
RW
RW
Rev. A | Page 71 of 75