AD7761_17 Datasheet, PDF (55/76 Pages) Analog Devices – 8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW

AD7761
Figure 78 shows an example of daisy-chaining AD7761 devices,
when FORMATx = 01. In this case, the DOUT1 and DOUT0 pins
of the AD7761 devices are cascaded to the DOUT6 and DOUT7
pins of the next device in the chain. Data readback is analogous
to clocking a shift register where data is clocked out on the rising
edge of DCLK. Input data on the DOUT6 and DOUT7 pins is
sampled on the falling edge of DCLK.
The scheme operates by passing the output data of the DOUT0
and DOUT1 pins of an AD7761 upstream device to the DOUT6
and DOUT7 inputs of the next AD7761 device downstream in the
chain. The data then continues through the chain until it is clocked
onto the DOUT0 and DOUT1 pins of the final downstream
device in the chain.
Daisy-chaining can be achieved in a similar manner on the
AD7761 when using only the DOUT0 pin. In this case, only
Pin 21 of the AD7761 is used as the serial data input pin.
In a daisy-chained system of AD7761 devices, two successive
synchronization pulses must be applied to guarantee that all ADCs
are synchronized. Two synchronization pulses are also required in a
system of more than one AD7761 device sharing a single MCLK
signal, where the DRDY pin of only one device is used to detect
new data.
The maximum DCLK frequency that can be used when daisy-
chaining devices is a function of the AD7761 timing specifications
(t4, and t11 in Table 4), the MCLK duty cycle, and any timing
differences between the AD7761 devices due to layout and spacing
of devices on the PCB.
Use the following formula to aid in determining the maximum
operating frequency of the interface:
( ) ^{f MAX}
=
2×
t ₁₁
+ t₄
1
+ t_P
+ t _SKEW
where:
fMAX is the maximum useable DCLK frequency.
t11 and t4 are the AD7761 timing specifications (see Table 4).
tP is the maximum propagation delay of the data between
successive AD7761 devices in the chain.
tSKEW is the maximum skew in the MCLK signal seen by any pair of
AD7761 devices in the chain.
The MCLK duty cycle is 50:50, or DCLK is set to MCLK/2,
MCLK/4, or MCLK/8.
In the case where the MCLK duty cycle is not 50:50 and the
interface is configured with DCLK = MCLK/1, ensure that the
applied MCLK signal meets the minimum MCLK high pulse width
requirement, as calculated by the following formula:
MCLK Minimum High Pulse Width = t11 + t4 + tP + tSKEW
Data Sheet
Synchronization
An important consideration for daisy-chaining more than two
AD7761 devices is synchronization. The basic provision for
synchronizing multiple devices is that each device is clocked
with the same base MCLK signal.
The AD7761 offers three options to allow ease of system synchro-
nization. Choosing between the options depends on the system, but
is determined by whether the user can supply a synchronization
pulse that is truly synchronous with the base MCLK signal.
If the user cannot provide a signal that is synchronous to the
base MCLK signal, one of the following two methods can be
employed:
• Apply a START pulse to the first AD7761 device. The first
AD7761 device samples the asynchronous START pulse
and generates a pulse on SYNC_OUT of the first device
related to the base MCLK signal for distribution locally.
• Use synchronization over SPI (only available in SPI control
mode) to write a synchronization command to the first
AD7761 device. Similarly to the START pin method, the
SPI sync generates a pulse on SYNC_OUT of the first device
related to the base MCLK signal for distribution locally.
In both cases, route the SYNC_OUT pin of the first device to
the SYNC_IN pin of that same device and to the SYNC_IN pins
of all other devices that are to be synchronized (see Figure 79).
The SYNC_OUT pins of the other devices must remain open
circuit. Tie all unused START pins to a Logic 1 through pull-up
resistors.
MCLK
AD7761
START
SYNCHRONIZATION ^SYNC_OUT
LOGIC
DIGITAL FILTER
SYNC_IN
DRDY
DOUT0
DOUT1
MASTER
CLOCK
IOVDD
MCLK
AD7761
START
SYNCHRONIZATION ^{SYNC_OUT DNC}
LOGIC
DIGITAL FILTER
DNC
DRDY
SYNC_IN
DSP/
FPGA
Figure 79. Synchronizing Multiple AD7761 Devices Using SYNC_OUT
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