AD7761_17 Datasheet, PDF (1/76 Pages) Analog Devices – 8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW

Data Sheet
8-Channel, 16-Bit, Simultaneous Sampling
ADC with Power Scaling, 110.8 kHz BW
AD7761
FEATURES
Linear phase digital filter
Precision ac and dc performance
8-channel simultaneous sampling
256 kSPS ADC ODR per channel
97.7 dB dynamic range
110.8 kHz input bandwidth (−3 dB BW)
−120 dB THD, typical
±1 LSB INL, ±1 LSB offset error, ±5 LSB gain error
Optimized power dissipation vs. noise vs. input bandwidth
Low latency sinc5 filter
Wideband brick wall filter: ±0.005 dB ripple to 102.4 kHz
Analog input precharge buffers
Power supply
AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V
IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V
64-lead LQFP package, no exposed pad
Temperature range: −40°C to +105°C
Selectable power, speed, and input bandwidth
Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel
Median (half speed): 55.4 kHz BW, 27.5 mW per channel
Low power (lowest power): 13.8 kHz BW, 9.375 mW per
channel
Input BW range: dc to 110.8 kHz
Programmable input bandwidth/sampling rates
CRC error checking on data interface
Daisy-chaining
APPLICATIONS
Data acquisition systems: USB/PXI/Ethernet
Instrumentation and industrial control loops
Audio testing and measurement
Vibration and asset condition monitoring
3-phase power quality analysis
Sonar
High precision medical electroencephalogram (EEG)/
electromyography (EMG)/electrocardiogram (ECG)
FUNCTIONAL BLOCK DIAGRAM
AVDD1A,
AVDD1B REFx+ REFx–
AVDD2A, REGCAPA,
AVDD2B REGCAPB DGND IOVDD DREGCAP
VCM
BUFFERED
VCM
VCM
PRECHARGE
×8
REFERENCE
BUFFERS
1.8V
LDO
AIN0+
P
CH 0
AIN0–
P
AIN1+
P
CH 1
AIN1–
P
AIN2+
P
CH 2
AIN2–
P
AIN3+
P
CH 3
AIN3–
P
AIN4+
P
CH 4
AIN4–
P
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
ADC
DIGITAL
FILTER
ENGINE
SINC5
LOW LATENCY
FILTER
WIDEBAND
LOW RIPPLE
FILTER
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
1.8V
LDO
ADC
OUTPUT
DATA
SERIAL
INTERFACE
SYNC_IN
SYNC_OUT
START
RESET
FORMAT1
FORMAT0
DRDY
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
AIN5+
P
CH 5
AIN5–
P
AIN6+
P
CH 6
AIN6–
P
Σ-Δ
ADC
Σ-Δ
ADC
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
SPI
CONTROL
INTERFACE
ST0/CS
ST1/SCLK
DEC0/SDO
DEC1/SDI
AIN7+
CH 7
AIN7–
P
Σ-Δ
P
ADC
×16 ANALOG INPUT
PRECHARGE BUFFERS (P)
OFFSET,
GAIN PHASE
CORRECTION
AD7761
PIN/SPI
AVSS
XTAL2/MCLK
Figure 1.
XTAL1
MODE3/GPIO3 FILTER/GPIO4
TO
MODE0/GPIO0
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2016–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com