AD9992 Datasheet, PDF (71/92 Pages) Analog Devices – 12-Bit CCD Signal Processor with Precision Timing Generator

AD9992
MASTER CLOCK INPUT
(1.8V LOGIC)
ANALOG OUTPUT FROM CCD
0.1µF
SERIAL INTERFACE ³
(FROM ASIC/DSP)
0.1µF
0.1µF
0.1µF
GENERAL-PURPOSE
OUTPUTS
8
GPO8 _A1
GPO7 _B2
GPO6 _C2
GPO5 _B1
GPO4 _B4
GPO3 _C1
GPO2 _D2
GPO1 _C3
EXTERNAL RESET IN
RSTB _E7
EXTERNAL SYNC IN
SYNC _D3
VERTICAL SYNC IN/OUT
HORIZONTAL SYNC IN/OUT
+1.8V DIGITAL I/O
VD _E2
HD _D1
IOVDD _E6
XV SUPPLY
IOVSS _E5
0.1µF
XVVDD _E3
XSUBCK _E1
XV1 _F2
XSUBCK OUTPUT
(TO V-DRIVER)
XV2 _F3
XV3 _F7
XV4 _G3
XV5 _F5
XV6 _F6
XV7 _G2
XV8 _F1
XV9 _G1
XV10 _G5
XV11 _H2
XV12 _H1
XV13 _G6
XV14 _G7
XV15 _J2
XV16 _J1
0.1µF
+1.8V SUPPLY
+1.8V SUPPLY
+3V CP OUTPUT
0.1µF
RG TO CCD
HL TO CCD
AD9992BBCZ
NOT DRAWN TO SCALE
A10 ^H8
B10 ^H7
A11 ^HVDD2
B11 ^HVSS2
0.1µF
H7, H8 TO CCD
+3V CP OUTPUT
C9 ^H6
D9 ^H5
H5, H6 TO CCD
C10 ^H4
D10 ^H3
H3, H4 TO CCD
C11 ^HVDD1
+3V CP OUTPUT
D11 ^HVSS1
E9 ^H2
0.1µF
F9 ^H1
E10 ^LDOIN
H1, H2 TO CCD
E11 ^LDOOUT
F11 ^SENSE
F10 ^LDO1P8EN
G9 ^LDOVSS
G11 ^LDO3P2EN
G10 ^NC
H9 ^CPCLI
H11 ^CP1P8
H10 ^CPVSS
+1.8V CP INPUT
0.1µF
J11 ^CPFCB
J10 ^CPFCT
0.1µF
K11 ^CP3P3
L11 ^DRVDD
K10 ^DRVSS
+3V CP OUTPUT
3.3µF
0.1µF
+1.8V DIGITAL SUPPLY
24 _{VERTICAL OUTPUTS}
(TOV-DRIVER)
+1.8V SUPPLY
0.1µF
DCLK OUTPUT
12
DATA OUTPUTS
Figure 81. Typical 1.8 V Circuit Configuration Using Charge Pump for HVDD and RGVDD
AD9992
~7MΩ
375Ω
K7
K6
CLI
USER DEFINED
CLO
5pF ~ 20pF
24MHz TO 40MHz
5pF ~ 20pF
XTAL
Figure 82. Crystal Application Using CLI/CLO (Consult Crystal Data Sheet for Component Values)
Rev. C | Page 71 of 92