AD9992 Datasheet, PDF (38/92 Pages) Analog Devices – 12-Bit CCD Signal Processor with Precision Timing Generator

AD9992
Special Pattern Insertion
Additional flexibility is available using the SPC_PAT_EN registers,
which allows a Group B, Group C, or Group D pattern to be
inserted into a series of Group A repetitions. This feature is
useful when a different pattern is needed at the start, end, or
middle of a sequence.
Figure 46 shows an example of a sweep region using VPATA
with multiple repetitions where a single repetition of VPATB has
been added into the middle of the sequence. Figure 47 shows more
detail on how to set the registers to achieve the desired timing.
Note that VREPB is used to specify which repetition number
has the special pattern inserted instead of VPATA. VPATB
always has priority over VPATC or VPATD if more than one
SPC_PAT_EN bit is enabled (SPC_PAT_EN [0] has priority).
VD
HD
XV1 TO XV24
LINE 0
SCP1
LINE 1
LINE 2
SCP2
LINE 24
LINE 25
REGION 0
REGION 1: SWEEP REGION
PATTERN B INSERTED DURING PATTERN A REPETITIONS
Figure 46. Example of Special Pattern Insertion
REGION 2
HD
REP 1
REP 2
REP 3
XV1
REP 4
REP 5
V-PATTERN A
V-PATTERN B
V-PATTERN A
REGISTER SETTINGS:
SPC_PAT_EN[0] = 1
VREPA = N
VREPB = 4
DESCRIPTION:
V-PATTERN B IS USED AS SPECIAL PATTERN
TOTAL NUMBER OF REPS USED FOR SEQUENCE (N REPS)
REP 4 USES V-PATTERN B INSTEAD OF V-PATTERN A
NOTES
1. VSTARTB MUST BE SET EQUAL TO VSTARTA.
Figure 47. Example of Special Pattern Insertion, Detail
REP N
Rev. C | Page 38 of 92