AD9691 Datasheet, PDF (71/72 Pages) Analog Devices – 14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter

Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
The AD9691 must be powered by the following seven supplies:
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR =
1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.8 V.
For applications requiring an optimal high power efficiency and
low noise performance, it is recommended that the ADP2164
and ADP2370 switching regulators be used to convert the 3.3 V,
5.0 V, or 12 V input rails to an intermediate rail (1.8 V and 3.8 V).
These intermediate rails are then postregulated by very low
noise, low dropout (LDO) regulators (ADP1741, ADP1740, and
ADP125). Figure 83 shows the recommended power supply
scheme for AD9691.
3.3V
INPUT
ADP1741
LDO
2.5V: AVDD2
ADP2164 _1.8V
BUCK
REGULATOR
ADP125
LDO
ADP1741
LDO
1.8V: SPIVDD
1.25V: AVDD1
ADP125
LDO
1.25V: AVDD1_SR
ADP1741
LDO
1.25V: DVDD
ADP1740
LDO
1.25V: DRVDD
5V/12V
INPUT
ADP2370 _3.8V
BUCK
REGULATOR
ADP125
LDO
3.3V: AVDD3
Figure 83. High Efficiency, Low Noise Power Solution for the AD9691
It is not necessary to split all of these power domains in all
cases. The recommended solution shown in Figure 83 provides
the lowest noise, highest efficiency power delivery system for
the AD9691. If only one 1.25 V supply is available, route to AVDD1
first and then tap it off and isolate it with a ferrite bead or a filter
choke, preceded by decoupling capacitors for AVDD1_SR,
SPIVDD, DVDD, and DRVDD, in that order. The user can
employ several different decoupling capacitors to cover both
high and low frequencies. These must be located close to the
point of entry at the PCB level and close to the devices, with
minimal trace lengths.
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
It is required that the exposed pad on the underside of the ADC
be connected to ground to achieve the best electrical and thermal
performance of the AD9691. Connect an exposed continuous
copper plane on the PCB to the AD9691 exposed pad, Pin 0.
AD9691
The copper plane must have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow
through the bottom of the PCB. These vias must be solder filled
or plugged. The number of vias and the fill determine the
resultant θJA measured on the board. This is shown in Table 7.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This
provides several tie points between the ADC and PCB during
the reflow process, whereas using one continuous plane with no
partitions only guarantees one tie point. See Figure 84 for a
recommended PCB layout example. For detailed information
on packaging and the PCB layout of chip scale packages, see the
AN-772 Application Note, A Design and Manufacturing Guide
for the Lead Frame Chip Scale Package (LFCSP).
Figure 84. Recommended PCB Layout of Exposed Pad for the AD9691
AVDD1_SR (PIN 78) AND AGND (PIN 77 AND PIN 81)
AVDD1_SR (Pin 78) and AGND (Pin 77 and Pin 81) can be
used to provide a separate power supply node to the SYSREF±
circuits of AD9691. If running in Subclass 1, the AD9691 can
support periodic one-shot or gapped signals. To minimize the
coupling of this supply into the AVDD1 supply node, adequate
supply bypassing is needed.
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