AD9691 Datasheet, PDF (45/72 Pages) Analog Devices – 14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter

Data Sheet
JESD204B LINK ESTABLISHMENT
The AD9691 JESD204B transmitter (Tx) interface operates in
Subclass 1 as defined in the JEDEC Standard JESD204B (July
2011 specification). The link establishment process is divided
into the following steps: code group synchronization and
SYNCINB±, initial lane alignment sequence, and user data and
error correction.
Code Group Synchronization (CGS) and SYNCINB±
The CGS is the process by which the JESD204B receiver finds
the boundaries between the 10-bit symbols in the stream of
data. During the CGS phase, the JESD204B transmit block
transmits the /K28.5/ characters. The receiver must locate the
/K28.5/ characters in its input data stream using clock and data
recovery (CDR) techniques.
The receiver issues a synchronization request by asserting the
SYNCINB± pin of the AD9691 low. The JESD204B Tx then
begins sending /K/ characters. After the receiver is synchronized,
it waits for the correct reception of at least four consecutive /K/
symbols. It then deasserts SYNCINB±. The AD9691 then
transmits an ILAS on the following local multiframe clock
(LMFC) boundary.
For more information on the code group synchronization
phase, refer to the JEDEC Standard JESD204B, July 2011,
Section 5.3.3.1.
The SYNCINB± pin operation can also be controlled by the
SPI. The SYNCINB± signal is a differential LVDS mode signal
by default, but it can also be driven single-ended. For more
information on configuring the SYNCINB± pin operation,see
Register 0x572 in Table 35.
AD9691
Initial Lane Alignment Sequence (ILAS)
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary. The ILAS consists of four multiframes, with
an /R/ character marking the beginning and an /A/ character
marking the end. The ILAS begins by sending an /R/ character
followed by 0 to 255 ramp data for one multiframe. On the second
multiframe, the link configuration data is sent, starting with the
third character. The second character is a /Q/ character to confirm
that the link configuration data follows. All undefined data slots
are filled with ramp data. The ILAS sequence is never scrambled.
The ILAS sequence construction is shown in Figure 73. The
four multiframes include the following:
• Multiframe 1, which begins with an /R/ character (/K28.0/)
and ends with an /A/ character (/K28.3/).
• Multiframe 2, which begins with an /R/ character followed
by a /Q/ (/K28.4/) character, followed by link configuration
parameters over 14 configuration octets (see Table 24) and
ends with an /A/ character. Many of the parameter values
are of the value – 1 notation.
• Multiframe 3, which begins with an /R/ character (/K28.0/)
and ends with an /A/ character (/K28.3/).
• Multiframe 4, which begins with an /R/ character (/K28.0/)
and ends with an /A/ character (/K28.3/).
KKRD
DARQC
CD
DARD
DARD
DAD
END OF
MULTIFRAME
START OF
ILAS
START OF LINK
CONFIGURATION DATA
Figure 73. Initial Lane Alignment Sequence
START OF
USER DATA
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