AD9691 Datasheet, PDF (62/72 Pages) Analog Devices – 14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter

AD9691
Data Sheet
Reg
Addr
(Hex)
0x249
0x24A
0x24B
0x24C
0x26F
0x270
0x271
0x272
0x273
0x274
0x275
0x276
0x277
0x278
0x279
0x27A
Register
Name
FD lower
threshold LSB
(local)
FD lower
threshold MSB
(local)
FD dwell time
LSB (local)
FD dwell time
MSB (local)
Signal monitor
synchronizatio
n control
Signal monitor
control (local)
Signal Monitor
Period
Register 0
(local)
Signal Monitor
Period
Register 1
(local)
Signal Monitor
Period
Register 2
(local)
Signal monitor
result control
(local)
Signal Monitor
Result
Register 0
(local)
Signal Monitor
Result
Register 1
(local)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Fast detect lower threshold, Bits[7:0]
Bit 1
Bit 0 (LSB)
0
0
0
Fast detect lower threshold, Bits[12:8]
Fast detect dwell time, Bits[7:0]
Fast detect dwell time, Bits[15:8]
0
0
0
0
0
0
Synchronization mode
00 = disabled
01 = continuous
11 = one-shot
0
0
0
0
0
0
Peak
0
detector
0=
disabled
1=
enabled
Signal monitor period, Bits[7:0]
Signal monitor period, Bits[15:8]
Signal monitor period, Bits[23:16]
0
0
0
Result
0
0
0
Result
update
selection
1 = update
0 = reserved
results (self
1 = peak
clear)
detector
Signal monitor result, Bits[7:0]
When Register 0x274, Bit 0 = 1, result Bits[19:7] = peak detector absolute value, Bits[12:0]; result Bits[6:0] = 0
Signal monitor result, Bits[15:8]
Signal Monitor 0
Result
Register 1
(local)
0
0
0
Signal monitor result, Bits[19:16]
Signal monitor
period
counter result
(local)
Period count result, Bits[7:0]
Signal monitor 0
SPORT over
JESD204B
control (local)
SPORT over 0
JESD204B
input
selection
(local)
0
0
0
0
0
0
0
0
0
0
Rev. 0 | Page 62 of 72
00 = reserved
11 = enable
Peak
0
detector
0=
disabled
1=
enabled
Default Notes
0x00
0x00
0x00
0x00
0x00
0x00
See the
Signal
Monitor
section
0x80
0x00
0x00
0x01
In
decimated
output
clock cycles
In
decimated
output
clock cycles
In
decimated
output
clock cycles
Read
only
Read
only
Read
only
Read
only
0x00
Updated
based on
Reg. 0x274,
Bit 4
Updated
based on
Reg.
0x274,
Bit 4
Updated
based on
Reg.
0x274,
Bit 4
Updated
based on
Reg.
0x274,
Bit 4
0x00