AD9691 Datasheet, PDF (67/72 Pages) Analog Devices – 14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter

Data Sheet
AD9691
Reg
Addr
(Hex)
0x571
0x572
0x573
0x574
0x578
0x580
0x581
0x583
0x584
0x585
0x586
0x587
0x588
0x589
0x58A
Register
Name
JESD204B Link
Mode Control 1
JESD204B Link
Mode Control 2
JESD204B Link
Mode Control 3
JESD204B Link
Mode Control 4
JESD204B
LMFC offset
JESD204B DID
config
JESD204B BID
config
JESD204B LID
Config 1
JESD204B LID
Config 2
JESD204B LID
Config 3
JESD204B LID
Config 4
JESD204B LID
Config 5
JESD204B LID
Config 6
JESD204B LID
Config 7
JESD204B LID
Config 8
Bit 7
(MSB)
Standby
mode
0 = all
converter
outputs 0
1 = CGS
(/K28.5/)
Bit 6
Tail bit (t)
PN
0=
disable
1=
enable
T = N΄ −
N − CS
SYNCINB± pin control
00 = normal
10 = ignore SYNCINB±
(force CGS)
11 = ignore SYNCINB±
(force ILAS/user data)
CHKSUM mode
00 = sum of all 8-bit
link config registers
01 = sum of individual
link config fields
10 = checksum set to
zero
Bit 5
Bit 4
Long
transpor
t layer
test
0=
disable
1=
enable
Lane
synchro-
nization
0 = disable
FACI uses
/K28.7/
1 = enable
FACI uses
/K28.3/ and
/K28.7/
SYNC-
INB± pin
invert
0=
active
low
1=
active
high
SYNCINB±
pin type
0=
differential
1 = CMOS
Test injection point
00 = N΄ sample input
01 = 10-bit data at
8B/10B output (for PHY
testing)
10 = 8-bit data at
scrambler input
ILAS delay
0000 = transmit ILAS on first LMFC after
SYNCINB± deasserted
0001 = transmit ILAS on second LMFC after
SYNCINB± deasserted
…
1111 = transmit ILAS on 16^th LMFC after
SYNCINB± deasserted
0
0
0
Bit 3
Bit 2
ILAS sequence mode
00 = ILAS disabled
01 = ILAS enabled
11 = ILAS always on
test mode
Bit 1
FACI
0=
enabled
1=
disabled
Bit 0 (LSB)
Link control
0 = active
1 = power
down
0
8B/10B
8B/10B bit 0
bypass
invert
0=
0=
normal
normal
1 = bypass 1 = invert
the a to j
symbols
JESD204B test mode patterns
0000 = normal operation (test mode disabled)
0001 = alternating checker board
0010 = 1/0 word toggle
0011 = 31-bit PN sequence—x³¹ + x²⁸ + 1
0100 = 23-bit PN sequence—x²³ + x¹⁸ + 1
0101 = 15-bit PN sequence—x¹⁵ + x¹⁴ + 1
0110 = 9-bit PN sequence—x⁹ + x⁵ + 1
0111 = 7-bit PN sequence—x⁷ + x⁶ + 1
1000 = ramp output
1110 = continuous/repeat user test
1111 = single user test
0
Link layer test mode
000 = normal operation (link layer test
mode disabled)
001 = continuous sequence of /D21.5/
characters
100 = modified RPAT test sequence
101 = JSPAT test sequence
110 = JTSPAT test sequence
LMFC phase offset value, Bits[4:0]
JESD204B Tx device ID (DID) value, Bits[7:0]
0
0
0
0
JESD204B Tx bank ID (BID) value, Bits[3:0]
0
0
0
Lane 0 lane ID (LID) value, Bits[4:0]
0
0
0
Lane 1 LID value, Bits[4:0]
0
0
0
Lane 2 LID value, Bits[4:0]
0
0
0
Lane 3 LID value, Bits[4:0]
0
0
0
Lane 4 LID value, Bits[4:0]
0
0
0
Lane 5 LID value, Bits[4:0]
0
0
0
Lane 6 LID value, Bits[4:0]
0
0
0
Lane 7 LID value, Bits[4:0]
Default Notes
0x14
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Rev. 0 | Page 67 of 72