AD9522-0 Datasheet, PDF (70/84 Pages) Analog Devices – 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

AD9522-0
Reg.
Addr
(Hex) Bit(s) Name
Description
018 [0]
VCO calibration
now
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The
sequence to initiate a calibration follows: program to 0, followed by an IO_UPDATE bit (Register 0x232[0]);
then program to 1, followed by another IO_UPDATE bit (Register 0x232[0]). This sequence gives complete
control over when the VCO calibration occurs relative to the programming of other registers that can impact
the calibration (default = 0). Note that the VCO divider (Register 0x1E0[2:0]) must not be static during VCO
calibration.
019 [7:6] R, A, B counters [7]
SYNC pin reset ₀
[6] Action
0 Do nothing on SYNC (default).
0
1 Asynchronous reset.
1
0 Synchronous reset.
1
1 Do nothing on SYNC.
019 [5:3] R path delay R path delay, see Table 2 (default: 0x0).
019 [2:0] N path delay N path delay, see Table 2 (default: 0x0).
01A [7] Enable STATUS Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the
pin divider
R and N dividers.
[7] = 0; divide-by-4 disabled on the STATUS pin (default).
[7] = 1; divide-by-4 enabled on the STATUS pin.
01A [6] Ref freq monitor Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
threshold
frequency monitor’s detection threshold (see Table 17, REF1, REF2, and VCO frequency status monitor parameter).
[6] = 0; frequency valid if the frequency is above 1.02 MHz (default).
[6] = 1; frequency valid if the frequency is above 6 kHz.
01A [5:0] LD pin
control
Selects the signal that is connected to the LD pin.
[5] [4] [3] [2]
Level or
Dynamic
[1] [0] Signal Signal at LD Pin
000 0
0 0 LVL
Digital lock detect (high = lock; low = unlock, default).
000 0
0 1 DYN P-channel, open-drain lock detect (analog lock detect).
000 0
1 0 DYN N-channel, open-drain lock detect (analog lock detect).
000 0
1 1 HIZ
Tristate (high-Z) LD pin.
000 1
0 0 CUR Current source lock detect (110 μA when DLD is true).
0 XX X
X X LVL
Ground (dc); for all other cases of 0XXXXX not specified.
The selections that follow are the same as for REFMON.
100 0
100 0
0 0 LVL
0 1 DYN
Ground (dc).
REF1 clock (differential reference when in differential mode).
100 0
100 0
100 1
1 0 DYN
1 1 DYN
0 0 DYN
REF2 clock (N/A in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available in differential mode).
100 1
100 1
0 1 LVL
1 0 LVL
Status of selected reference (status of differential reference);
active high.
Status of unselected reference (not available in differential
mode); active high.
100 1
101 0
1 1 LVL
0 0 LVL
Status REF1 frequency (active high).
Status REF2 frequency (active high).
101 0
101 0
0 1 LVL
1 0 LVL
(Status REF1 frequency) AND (status REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
101 0
101 1
1 1 LVL
0 0 LVL
Status of VCO frequency (active high).
Selected reference (low = REF1, high = REF2).
101 1
0 1 LVL
DLD; active high.
101 1
1 0 LVL
Holdover active (active high).
101 1
1 1 LVL
N/A, do not use.
110 0
0 0 LVL
VS (PLL supply).
110 0
0 1 DYN REF1 clock (differential reference when in differential mode).
Rev. 0 | Page 70 of 84